Hardware Key Generator for Packet Parsing Latency
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Solution Overview
Problem
Network devices face inefficiencies in processing packets due to high latency and resource utilization, particularly in generating lookup keys from packet information, as existing methods rely heavily on software-based parsing and key generation, which are slow and resource-intensive.
Innovation Solution
A method and system for packet processing in network devices that involves a programmable processing unit to identify protocol layers and locations within packet headers, using hardware key generators to extract fields and create lookup keys, which are then used by lookup engines to perform operations, thereby reducing latency and improving resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based parsing and key generation is used, then flexibility in handling various packet formats is improved, but processing speed and latency are worsened
Solution Approach 1:
The packet processing system is divided into multiple protocol layer parsing units (L1-L3, L4-L6, L7) that operate in parallel. Each unit handles specific protocol layers independently, allowing simultaneous processing of different packet formats without sequential software intervention, thus improving both speed and flexibility.
Solution Approach 2:
A hardware key generator block acts as an intermediary between the protocol parsing units and the lookup engine. This dedicated hardware component receives parsed protocol information and automatically generates lookup keys through field extraction and concatenation operations, eliminating the need for software-based key generation and significantly improving processing speed.
2Productivity
If software-based key generation is used, then resource utilization is improved, but processing latency is worsened
Solution Approach 1:
The patent replaces the mechanical software-based key generation process with a dedicated hardware key generator block. This hardware implementation performs field extraction, masking, shifting, and concatenation operations in parallel at hardware speed, reducing processing latency by several orders of magnitude compared to software execution while maintaining efficient resource utilization through specialized circuitry.
3Speed
If hardware key generators are introduced, then processing speed is improved, but device complexity is worsened
Solution Approach 1:
The hardware key generator block is designed as a universal component that can generate lookup keys for multiple different packet formats and protocol combinations. It receives standardized parsed protocol information from various parsing units and applies configurable field extraction and concatenation rules, enabling it to handle diverse packet types through a single multi-functional hardware unit rather than requiring separate hardware for each packet format.
Data Source
AI summary
A packet being processed by a network device is parsed by a programmable processing unit executing computer readable instructions stored in a non-transitory computer readable storage medium. Parsing the packet includes identifying one or more protocol layers within a header of the packet, identifying respective locations of protocol headers within the header of the packet, and providing the respective identified locations of protocol headers within the header of the packet to a hardware key generator block. A lookup key corresponding to the packet is generated by the key generator block using the respective identified locations. Generating the lookup key includes extracting, using an identified location of a protocol header, one or more fields from the corresponding protocol header. The lookup key is provided to a lookup engine. A lookup operation with respect to the packet is performed by the lookup engine and based on the lookup key.