Hardware Layer Network Address Translation for High Speed
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Solution Overview
Problem
Current network address translation (NAT) technologies face bottlenecks in scalability and latency due to the re-circulation of packets during address translation, which affects load balancing and performance in high-speed network environments.
Innovation Solution
A method that configures a network device with a hardware layer, including a ternary content-addressable memory (TCAM) ASIC, to perform single clock cycle address translation by pre-defining layer 2 and 3 addresses and implementing policies for load balancing, allowing for efficient translation and redirection of packets without re-circulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional NAT translation is performed in software, then address translation functionality is achieved, but processing speed is slow and latency is high
Solution Approach 1:
The patent replaces software-based NAT translation with hardware-based translation using an Application-Specific Integrated Circuit (ASIC). This substitution moves the translation function from a software processing environment to a dedicated hardware circuit, enabling single-clock-cycle translation operations and eliminating the performance bottlenecks of software implementation.
Solution Approach 2:
The patent pre-configures the ASIC with translation rules, address mappings, and policy decisions before operation. By preparing all necessary translation data and decision logic in advance during device initialization, the system eliminates real-time lookup and decision-making delays, allowing packets to be translated immediately upon arrival without re-circulation.
2Loss of time
If packets are re-circulated multiple times for translation and address resolution, then accurate address translation is achieved, but latency increases and throughput decreases
Solution Approach 1:
The patent combines multiple separate translation and address resolution operations into a single integrated hardware process. The ASIC performs destination NAT, source NAT, and address resolution simultaneously in one clock cycle, eliminating the need for packets to traverse the system multiple times through different processing stages.
Solution Approach 2:
The patent introduces a hardware intermediary layer (the ASIC) that sits between the network interfaces and handles all translation operations. This intermediary captures packets directly from the network, performs complete translation in hardware, and forwards translated packets without requiring software intervention or repeated processing cycles.
3Adaptability or versatility
If dynamic address translation is implemented to handle server changes, then adaptability is improved, but processing speed decreases due to reconfiguration overhead
Solution Approach 1:
The patent implements dynamic reconfiguration capability in the ASIC, allowing translation rules and address mappings to be updated while the device operates. This dynamic feature enables the system to adapt to server additions, removals, or IP changes without requiring physical hardware changes, while maintaining high translation speeds through efficient reconfiguration protocols.
Data Source
AI summary
Embodiments include receiving configuration information including a match criterion for packets received at a network device in a network and a pool of layer 3 addresses associated with a set of servers in the network, resolving layer 2 destination addresses based on the layer 3 addresses of the servers, and programming a hardware layer of the network device based, at least in part, on the match criterion, the pool of layer 3 addresses, and the layer 2 destination addresses. Specific embodiments include configuring a policy to indicate that packets from an external source are to be forwarded to a server of the set of servers. Further embodiments include receiving a packet at the network device, and matching the packet to the pool of layer 3 addresses and the resolved layer 2 addresses based, at least in part, on the match criterion programmed in the hardware layer.