Hardware Link Timer for Low-Latency Ethernet Packet Replay
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Solution Overview
Problem
Existing Ethernet-based communication networks face challenges in achieving high bandwidth, low latency, and lossy resilience with minimal CPU involvement, particularly in high-performance computing and AI training data centers, due to limitations in flow control protocols and software overhead.
Innovation Solution
Implementing a hardware-only Ethernet protocol with a hardware replay architecture and state machine to manage packet transmission and retransmission, utilizing a hardware link timer and FIFO memory to achieve low latency and lossy resilience, without software assistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TCP/IP protocols are used for Ethernet communication, then flow control is achieved, but latency increases to the order of milliseconds
Solution Approach 1:
The patent extracts the flow control functionality from software-based TCP/IP protocols and implements it in hardware at the Ethernet layer. This separation removes the software overhead and CPU involvement that cause millisecond-level latency, while preserving the essential flow control capability through hardware-based packet tracking and retransmission mechanisms.
Solution Approach 2:
The patent replaces the software-based flow control mechanism with a hardware-based system using dedicated circuits, FIFO buffers, and state machines. This substitution eliminates the interpretation overhead of software protocols and achieves microsecond-level latency through direct hardware control of packet transmission and retransmission.
2Reliability
If RoCE or InfiniBand protocols are used, then lossless and scaling specifications are achieved, but system constraints increase
Solution Approach 1:
The patent employs a simpler, more disposable approach to reliability by using hardware-based packet tracking and retransmission without the complex scaling specifications of RoCE or InfiniBand. The system accepts packet loss and recovers through hardware retransmission, avoiding the overhead of maintaining complex lossless specifications across scaled networks.
3Reliability
If software assistance is used for Ethernet protocol implementation, then protocol compliance is achieved, but CPU involvement increases
Solution Approach 1:
The patent implements self-service by creating a hardware-based Ethernet protocol engine that autonomously handles packet transmission, flow control, and retransmission without CPU involvement. The hardware system independently manages protocol compliance through dedicated circuits and state machines, freeing the CPU from protocol processing tasks.
4Reliability
If hardware replay architecture is implemented, then packet retransmission is achieved, but device complexity increases
Solution Approach 1:
The patent segments the replay architecture into distinct hardware components: FIFO buffers for packet storage, timers for retransmission scheduling, and control logic for managing the replay process. This segmentation organizes the complexity into manageable modules while achieving lossy resilience through coordinated hardware operation.
Data Source
AI summary
The present disclosure relates to systems and methods for communicating in an Ethernet-based network using a transport layer without assistance of software-controlled mechanisms. In some embodiments, a first node includes a hardware link timer configured to determine packets transmitted under the transport layer hardware only Ethernet protocol to replay. The hardware link timer can include a first-in-first-out (FIFO) memory configured to store timing and status information associated with one or more links established by the first node. The hardware link timer can further include a timer associated with the one or more links that ticks according to a time period.