Hardware LZMA Compression Using Parallel Forward and Backward Passes

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Solution Overview

Problem

Software-based Lempel-Ziv-Markov chain algorithm (LZMA) compression processes are time-consuming, limiting their application despite achieving high compression quality.

Innovation Solution

Implementing LZMA compression engines with hardware accelerators, including field-programmable gate array (FPGA) devices, to perform both forward and backward pass compression processes in parallel, alongside range or Huffman encoding, to enhance compression efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If LZMA compression is implemented in software, then compression quality is high, but compression time is long

Engineering Contradiction:
Improvecompression qualityVSAvoidcompression time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent replaces the software-based LZMA compression system with a hardware-based system using FPGAs and ASICs. This substitution of the execution medium (from software to hardware) enables parallel processing of the forward and backward passes, dramatically reducing compression time while preserving the algorithm's high compression quality characteristics.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent divides the LZMA compression process into two separate hardware processors: one dedicated to the forward pass and another to the backward pass. This segmentation allows both passes to execute simultaneously in parallel, eliminating the sequential execution bottleneck present in software implementations and significantly accelerating the overall compression process.

Inventive Principle:
Principle #1Segmentation

2Loss of time

If hardware accelerators are used for LZMA compression, then compression time is reduced, but device complexity increases

Engineering Contradiction:
Improvecompression timeVSAvoiddevice complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent designs the hardware compression system to be universally applicable across different platforms and data types. The FPGA-based architecture can be configured for various compression scenarios, and the system supports multiple encoding modes (forward pass, backward pass, and combined), making the complex hardware investment worthwhile through versatile functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines multiple compression functions (LZMA forward pass, LZMA backward pass, range encoding, and Huffman encoding) into a single integrated hardware system. By merging these functions into one unified device, the patent reduces the need for multiple separate components, thereby managing device complexity while achieving parallel execution and high compression speed.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If parallel processing is implemented for LZMA compression, then productivity increases, but device complexity increases

Engineering Contradiction:
Improvecompression speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the LZMA compression algorithm into two independent but complementary passes (forward and backward), each implemented in separate hardware processors. This segmentation enables true parallel execution where both passes can operate simultaneously on different portions of the data, dramatically increasing compression productivity while keeping each individual processor relatively simple in design.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10565182B2Hardware LZMA compressor
Publication Date: 2020.02.18 MICROSOFT TECHNOLOGY LICENSING LLC
  • US10565182B2 patent drawing
  • US10565182B2 patent drawing
  • US10565182B2 patent drawing

AI summary

A system is provided that includes a first processor and a second processor. The first processor includes first hardware logic circuitry that performs a Lempel-Ziv-Markov chain algorithm (LZMA) forward pass compression process on a portion of source data to provide first output data. The second processor that performs an LZMA backward pass compression process on the first output data to provide second output data.