Hardware Memory Access Telemetry Tracking

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Solution Overview

Problem

Conventional software-based methods for tracking memory access telemetry suffer from high latency and overhead, making it difficult to make timely data placement adjustments to maintain optimum performance in systems with increasing non-uniform memory access.

Innovation Solution

A hardware-based solution that uses a counting Bloom filter front-end, a pipeline for sorting and filtering access tuples, and an output array to generate accurate and timely page access frequency telemetry at a specified granularity, such as operating system page granularity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If software-based methods are used for tracking memory access telemetry, then implementation complexity is reduced, but latency and overhead increase making timely data placement adjustments difficult

Engineering Contradiction:
Improveimplementation complexityVSAvoidlatency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent replaces software-based tracking mechanisms with hardware-based tracking logic integrated into the memory controller. This substitution of mechanical/software system with hardware system reduces latency and overhead while enabling timely data placement adjustments, directly resolving the contradiction between implementation complexity and time loss.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Loss of time

If hardware-based tracking is implemented, then latency and overhead are reduced, but device complexity increases

Engineering Contradiction:
ImprovelatencyVSAvoiddevice complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges the tracking logic directly into the memory controller hardware, combining multiple functions (memory control and access tracking) into a single integrated device. This merging approach reduces the need for separate hardware components and software layers, thereby reducing overall device complexity while achieving low-latency hardware-based tracking.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory controller is designed to perform multiple functions: traditional memory control operations and memory access telemetry tracking. By making the memory controller universal and multi-functional, the patent avoids adding separate dedicated tracking hardware, thus reducing device complexity while achieving hardware-based low-latency tracking.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If page granularity tracking is implemented, then measurement precision is improved, but quantity of data to be processed increases

Engineering Contradiction:
Improveaccess telemetry granularityVSAvoiddata volume
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent extracts and counts only the essential telemetry data at page granularity level using hardware tracking logic, filtering out unnecessary detailed information. This extraction approach maintains high measurement precision at page level while minimizing the quantity of data that needs to be processed and transmitted, resolving the contradiction between precision and data volume.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250138732A1Hardware tracking of memory accesses
Publication Date: 2025.05.01 RAMBUS INC
  • US20250138732A1 patent drawing
  • US20250138732A1 patent drawing
  • US20250138732A1 patent drawing

AI summary

Technologies for hardware-based memory access telemetry tracking are described. A receiver circuit includes analog and digital circuitry. A memory controller includes a processing pipeline with a first processing stage to update and record a first number of access counts targeting a logical grouping of memory locations and a second processing stage to continuously sort the first number of access counts and their associated address tags corresponding to the logical grouping of memory locations, keeping only the access counts with unique address tags.