Hardware Memory Assistant for Remote Transactional Memory Coherency
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Solution Overview
Problem
In memory-centric computing, maintaining memory data consistency and cache coherency across multiple access points in remote shared memory systems is challenging, leading to high overhead in cache coherency maintenance and potential performance issues.
Innovation Solution
The implementation of hardware-assisted remote transactional memory, where memory instructions from remote processors are queued and managed by hardware memory assistants, which compare memory addresses and abort transactions that overlap, ensuring coherency with minimal overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherency maintenance protocol is implemented over fabric in remote shared memory systems, then memory data consistency is maintained, but memory sharing performance is impacted due to high volume protocol overhead
Solution Approach 1:
The patent extracts the cache coherency maintenance function from the fabric communication protocol and implements it locally within the remote processor's interconnect fabric. This allows coherency checks to be performed without generating high-volume protocol traffic over the external fabric, thus maintaining memory data consistency while improving memory sharing performance by eliminating protocol overhead
Solution Approach 2:
The patent introduces an intermediary component (coherency management logic within the remote processor) that handles cache coherency maintenance locally. This intermediary processes coherency requests internally before accessing external memory, preventing the propagation of high-volume coherency protocols over the fabric and thereby maintaining both consistency and performance
2Productivity
If multiple remote processors access shared memory simultaneously, then system throughput is improved, but cache coherency issues arise leading to potential data inconsistency
Solution Approach 1:
The patent implements preliminary action by performing cache coherency validation checks before allowing remote processor access to shared memory. The coherency management logic validates access requests against the memory transaction queue and coherency state before permitting memory operations, thus preventing coherency issues before they occur while allowing multiple processors to access memory concurrently
Solution Approach 2:
The patent implements feedback mechanisms where the coherency management logic continuously monitors memory access patterns and queue states, and dynamically adjusts access permissions for remote processors. This feedback loop ensures that coherency is maintained while maximizing throughput by allowing valid concurrent accesses and blocking only those that would cause conflicts
3Productivity
If hardware memory assistants queue and manage memory transactions, then transaction management efficiency is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the hardware memory assistant to perform multiple functions: queuing memory transactions, validating coherency, managing address translation, and controlling access permissions. By consolidating these diverse functions into a single multi-functional component, the patent improves transaction management efficiency while minimizing the increase in device complexity that would result from separate dedicated components for each function
Data Source
AI summary
Hardware assisted remote transactional memory including receiving, from a first remote processor over a high-speed communications fabric, an indication of a beginning of a first memory transaction; queuing, in a first hardware memory assistant, memory instructions for the first memory transaction; receiving, from a second remote processor over the high-speed communications fabric, an indication of a beginning of a second memory transaction; queuing, in a second hardware memory assistant, memory instructions for the second memory transaction; receiving, from the first remote processor over the high-speed communications fabric, an indication of an ending of the first memory transaction; comparing memory addresses accessed in the first memory transaction to memory addresses accessed in the second memory transaction; and in response to determining that the memory addresses accessed in the first memory transaction overlap with the memory addresses accessed in the second memory transaction, aborting the first memory transaction.