Hardware Memory Patching Circuit for ROM Bug Fixing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory patching solutions for non-volatile and volatile memories face limitations in scalability, silicon area requirements, and execution cycle consumption, particularly when attempting to replace defective code in ROM, as they either require significant additional code space or introduce delays in processing unit execution.
Innovation Solution
A memory patching circuit with a code generation unit, address memory, and distance calculator that dynamically generates and injects hardcoded assembly instructions to redirect execution flow, allowing for seamless patching of multiple memory positions with minimal silicon area and latency, using a table of pointers to replacement functions stored in SRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If software based patching mechanisms are used to replace defective code in ROM, then the ability to fix bugs after manufacturing is improved, but the code memory area requirement increases and execution cycles are consumed
Solution Approach 1:
The invention extracts only the essential patching functionality into a dedicated hardware circuit, removing the need for extensive software patching code. The patching logic is taken out from the software domain and implemented as hardwired comparison and multiplexing circuits, thereby eliminating the requirement for large software-based patching tables while maintaining bug-fix capability.
Solution Approach 2:
The invention introduces a hardware intermediary layer between the ROM and the processor that actively monitors address bus transactions and dynamically selects between original and patched code. This intermediary hardware circuit acts as a mediator that redirects execution flow without requiring software-based patching mechanisms, thus reducing code memory requirements.
2Ease of repair
If software based patching mechanisms are used to replace defective code in ROM, then the ability to fix bugs after manufacturing is improved, but the execution cycle time increases
Solution Approach 1:
The invention performs preliminary action by pre-configuring the hardware patching circuit with the patched code addresses before execution begins. The address comparison and code selection logic are prepared in advance through mask programming, allowing the processor to seamlessly switch between original and patched code without any runtime overhead or additional execution cycles.
Solution Approach 2:
The invention replaces the mechanical/software-based patching system with a hardware-based electronic system. The address comparison and code selection that would otherwise require software execution are performed by hardwired logic circuits operating in parallel with the processor, thereby eliminating the time penalty associated with software-based patching.
3Adaptability or versatility
If hardware based patching systems track all transactions on the system bus to replace defective code, then the ability to patch memory positions is improved, but the silicon area requirement increases
Solution Approach 1:
The invention applies local quality by implementing address masking that focuses the patching circuit's attention only on specific address bits relevant to the patched code locations. Rather than monitoring all address transactions uniformly, the circuit selectively compares only the necessary address portions, thereby reducing the complexity and silicon area of the comparison logic while maintaining the ability to patch specific memory positions.
Solution Approach 2:
The invention uses partial action by implementing selective address comparison rather than tracking all memory transactions. The patching circuit performs comparison only for addresses that match the patched code locations, using mask bits to enable or disable specific address comparisons. This partial monitoring approach reduces the silicon area required for the patching circuit while maintaining effective patching capability.
4Loss of time
If hardware based patching systems are used to replace defective code, then the execution delay is reduced, but the silicon area requirement increases
Solution Approach 1:
The invention segments the address comparison function into multiple independent comparison units, each handling a specific patched code location. By dividing the patching logic into discrete, modular segments, the circuit can use simple parallel comparison logic for each segment rather than a single complex comparison unit, thereby reducing overall silicon area while maintaining fast execution.
Solution Approach 2:
The invention merges the address comparison and code selection functions into a single integrated hardware circuit that operates in parallel with the processor. By combining these functions and using shared resources such as the address bus and data bus, the circuit achieves fast patching performance without requiring separate dedicated hardware for each function, thus reducing silicon area overhead.
Data Source
AI summary
A patching system and a patching circuit provide a type of patching entry which can replace several sequential memory positions with hardcoded and dynamically configured assembly instructions, thus injecting a small piece of code. The operation of the injected code can be for any purpose, but as an example may be used to seamlessly redirect the execution flow of a processing unit.