Hardware Memory Scrubbing for Data Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems rely on software or firmware solutions to detect and correct bit errors in RAM, which can lead to performance degradation and increased communication bandwidth usage, and are not practical for all memory storage spaces due to the need for processor intervention and accessibility.
Innovation Solution
An integrated circuit with a memory element and correction logic that performs error detection and correction during idle cycles, allowing for hardware-based scrubbing without processor intervention, using ECC bits to identify and correct correctable errors without disrupting normal RAM operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software or firmware solutions are used to detect and correct bit errors in RAM, then error correction capability is improved, but processor performance and communication bandwidth are degraded
Solution Approach 1:
The memory system performs self-diagnosis and self-correction through integrated correction logic that automatically detects and corrects bit errors using ECC bits during idle cycles, eliminating the need for processor intervention and preserving processor performance while maintaining error correction capability
Solution Approach 2:
The correction logic is separated from the processor and integrated directly into the memory system, allowing independent error correction operations that do not consume processor cycles or communication bandwidth
2Reliability
If software scrubbing techniques are employed to detect and correct bit errors, then error detection capability is improved, but communication bandwidth consumption increases
Solution Approach 1:
The memory system performs autonomous error detection and correction using integrated correction logic that operates independently without requiring data transfer over communication buses, thereby detecting errors while consuming minimal communication bandwidth
3Reliability
If all RAMs are made accessible by a processor core for error correction, then error correction coverage is improved, but system complexity and practicality are degraded
Solution Approach 1:
Each memory system incorporates integrated correction logic that enables autonomous error correction without processor accessibility, simplifying the system architecture while maintaining comprehensive error correction coverage across all RAM locations
Solution Approach 2:
The correction logic is extracted from the processor and embedded within the memory system, eliminating the requirement for processor core accessibility to all RAMs and reducing system complexity while preserving error correction functionality
Data Source
AI summary
Embodiments herein describe a hardware based scrubbing scheme where correction logic is integrated with memory elements such that scrubbing is performed by hardware. The correction logic reads the data words stored in the memory element during idle cycles. If a correctable error is detected, the correction logic can then use a subsequent idle cycle to perform a write to correct the error (i.e., replace the corrupted data stored in the memory element with corrected data). By using built-in or integrated correction logic, the embodiments herein do not add extra work for the processor, or can work with applications that do not include a processor. Further, because the correction logic scrubs the memory during idle cycles, correcting bit errors does not have a negative impact on the performance of the memory element. Memory scrubbing can delay the degradation of data error, extending the integrity of the data in the memory.