Hardware Message Queue Circuit for Virtual Processor Isolation
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Solution Overview
Problem
Existing methods for communicating information to inactive virtual processors in computer systems require hypervisor cycles, leading to diminished performance of executing virtual processors.
Innovation Solution
A hardware circuit is configured to transfer messages to a message queue in the operating system without using the operating system or hypervisor, by tying head and tail pointers and using a logical identifier to select entries in mapping and action tables, allowing messages to be appended directly to the queue without hypervisor intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hypervisor is used to transfer messages to inactive virtual processors, then message delivery is achieved, but processing cycles are stolen and performance of executing virtual processors diminishes
Solution Approach 1:
The patent extracts the message queue functionality from the hypervisor software layer and implements it directly in hardware within the processor. This allows message queues to be maintained and messages to be delivered to inactive virtual processors without requiring hypervisor intervention, thereby eliminating the performance penalty of stealing processor cycles while ensuring reliable message delivery.
Solution Approach 2:
The hardware circuit within the processor automatically manages message queues and delivers messages to inactive virtual processors without external control. The processor self-services the message delivery function through dedicated hardware structures including message queues, head/tail pointers, and mapping tables, eliminating dependency on hypervisor software for this critical function.
2Productivity
If hardware circuits are used to transfer messages directly without hypervisor intervention, then processing cycles are preserved and performance is enhanced, but system complexity increases
Solution Approach 1:
The patent integrates message queue functionality into the existing processor hardware structures, making the processor perform multiple functions - both general-purpose computation and specialized message queue management. By utilizing existing hardware resources and creating multi-functional components, the patent avoids adding separate dedicated hardware systems, thereby limiting the increase in overall system complexity.
3Loss of time
If message queues are maintained in hardware without hypervisor involvement, then hypervisor overhead is eliminated, but the complexity of hardware message management increases
Solution Approach 1:
The patent replaces the software-based hypervisor message management mechanism with a hardware-based automatic management system. The hardware circuit automatically performs queue operations including enqueueing messages, updating head and tail pointers, and delivering messages to inactive virtual processors, eliminating the time-consuming software intervention while managing complexity through dedicated hardware logic.
Data Source
AI summary
A computer-based method configures a hardware circuit to transfer a message to a message queue in an operating system. The hardware circuit is used to transfer a message to the message queue in the operating system without requiring use of either the operating system or a hypervisor associated with the operating system. The using the hardware circuit uses a logical identifier associated with the message to select an entry in a mapping table of the hardware circuit. A value in the entry in the mapping table is used to select an entry in an action table. The entry in the action table is used to determine a tail pointer for the message queue. The hardware circuit appends the message to a location indicted by the tail pointer without requiring cycles of a hypervisor associated with the strand.