Hardware Mutex Controller with Waiter Flag Cache
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Solution Overview
Problem
Existing mutex mechanisms in computer systems incur significant overhead in lock and unlock operations, especially under non-contending conditions, and require disabling processor interrupts, leading to latency and priority inversion issues.
Innovation Solution
A hardware-based mutex system with a locked mutex cache and dedicated registers for lock and unlock operations, which reduces overhead by silently setting or clearing flags without interrupting the system, and asserts interrupts only when necessary, thereby eliminating the need for global interrupt disabling and handling priority inversions efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software mutexes are used to protect shared resources, then resource access control is achieved, but processing time and system overhead increase significantly
Solution Approach 1:
The patent replaces the software-based mutex mechanism with a hardware-based mutex implementation. The hardware mutex uses dedicated hardware circuits including a mutex controller, lock register, unlock register, and wait queue register to manage resource access. This hardware substitution eliminates the need for software kernel involvement in routine lock/unlock operations, significantly reducing processing time while maintaining reliable resource access control through hardware-enforced mutual exclusion.
Solution Approach 2:
The hardware mutex system implements self-service by automatically managing the mutex state through hardware circuits. The mutex controller autonomously handles lock acquisition, unlock operations, and waiting tasks without requiring continuous software intervention. The hardware automatically checks lock status, manages wait queues, and enables interrupt-driven notification, allowing the system to service itself rather than relying on software mutex management.
2Ease of operation
If processor interrupts are globally disabled to manage mutexes, then mutex state checking is simplified, but latency increases and system responsiveness decreases
Solution Approach 1:
The patent replaces software-based mutex management with a hardware-based system that operates independently of interrupt state. The hardware mutex uses dedicated registers and circuits that can be read and modified without affecting processor interrupt status. The mutex controller directly manages lock state through hardware registers, eliminating the need to globally disable interrupts for mutex operations, thus maintaining system responsiveness while simplifying mutex state checking.
Solution Approach 2:
The hardware mutex introduces an intermediary layer between software tasks and the shared resource. The mutex controller acts as a mediator that manages access control through hardware circuits, isolating the software from the complexity of interrupt management. This intermediary hardware layer handles mutex state checking and control without requiring global interrupt disabling, allowing software tasks to operate with interrupts enabled while still achieving mutual exclusion.
3Manufacturing precision
If software mutexes are used with fine-grained locking, then resource access precision is improved, but overhead increases making it less economical
Solution Approach 1:
The patent replaces software-based fine-grained mutex management with a hardware-based system that provides precise resource access control without the overhead of software processing. The hardware mutex uses dedicated circuits to manage each mutex instance, enabling fine-grained locking at the hardware level. This eliminates the need for software kernel involvement in each lock/unlock operation, maintaining precise resource access while significantly reducing the overhead associated with fine-grained locking.
4Reliability
If priority inversion handling is implemented in software, then priority correctness is maintained, but implementation complexity and operational overhead increase
Solution Approach 1:
The patent replaces software-based priority inversion handling with a hardware-based mutex system that inherently prevents priority inversion issues. The hardware mutex uses dedicated circuits to manage mutex state and access control, eliminating the need for software-based priority inheritance protocols. By implementing mutual exclusion at the hardware level, the system prevents lower-priority tasks from holding locks that block higher-priority tasks, thereby maintaining priority correctness without the complexity of software-based priority management.
Data Source
AI summary
Hardware resources sharing for a computer system running software tasks. A controller stores records including a mutex ID tag and a waiter flag in a cache. Lock and unlock registers are readable by the controller and loadable by the tasks with a mutex ID specifying a hardware resource. The controller monitors whether the lock register for loading with a mutex ID, and then determines whether it corresponds with the tag of a record in the cache. If so, it sets the record's waiter flag. If not, it adds a record having a tag corresponding with the mutex ID. The controller also monitors whether the unlock register for loading with a mutex ID, and then determines whether it corresponds with the tag of a record in the cache. If so, it determines whether that record's waiter flag is set and, if so, it clears that record from the cache.