Hardware Neuromorphic System for STDP Synapse and LIF Neuron Simulation

The patent replaces software-based mathematical modeling with hardware-based electronic circuit implementation. The LIF neuron model is implemented using electronic circuits that naturally perform integration and threshold detection, while STDP synapse modeling is implemented using hardware logic circuits that compute weight updates based on spike timing differences. This substitution of software computation with hardware circuitry achieves real-time neuromorphic simulation with significantly improved computing speed.

The patent divides the neuromorphic system into distinct functional modules: LIF neuron model circuits for membrane potential simulation, STDP synapse model circuits for weight update computation, timer units for spike timing measurement, and a serial-to-parallel converter for data processing. Each module is implemented as a separate hardware component with dedicated functionality, making the complex system manageable through modular design while maintaining high operation speed.

The patent incorporates timer units that continuously track and measure the elapsed time between axon spikes and dendrite spikes in real-time. These timers perform the time measurement action preliminarily and continuously, so when a spike event occurs, the precise time difference is already available for immediate use in the STDP weight update computation, eliminating the need for complex post-processing time calculations.

The patent employs a serial-to-parallel converter that processes neuron fire data streams in periodic cycles, converting serial incoming data into parallel output formats at regular intervals. This periodic conversion approach enables efficient batch processing of spike events, allowing multiple neurons' fire data to be processed simultaneously in parallel, thereby improving overall data processing efficiency while using a relatively simple converter architecture.