Hardware NVMe Controller for Fast Non-Volatile Memory
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Solution Overview
Problem
Current firmware-based controllers for fast non-volatile memories like PRAM and MRAM suffer from performance bottlenecks due to high latency, which cannot be hidden behind CPU cycles, as they dominate the total service time, hindering the full potential of these advanced memory technologies.
Innovation Solution
A hardware-based non-volatile memory controlling device with a first and second doorbell region, a fetch managing module, a data transferring module, and a completion handling module, which automates I/O operations by exposing doorbell regions to the host interface, using advanced interfaces like PCIe and AXI buses, and implementing DMA engines to manage data transfers and interrupts, thereby reducing firmware execution time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If firmware-based controllers are used for fast non-volatile memories, then the memory interface and control logic are implemented in software, but the firmware execution time dominates the total service time and cannot be hidden behind CPU cycles, creating a performance bottleneck
Solution Approach 1:
The patent replaces the firmware-based control system with a hardware-based controller that implements NVMe protocol functions through dedicated hardware circuits. The controller includes a PCIe interface for host communication, an internal memory bus for data transfer, and hardware modules for command processing, data transfer, and completion handling, eliminating the need for firmware execution and thereby removing the performance bottleneck while maintaining protocol compliance and control flexibility
Solution Approach 2:
The patent introduces an intermediate hardware layer between the host and the non-volatile memory module. This hardware controller acts as a mediator that translates host commands into memory operations, managing data transfer and completion handling through dedicated hardware circuits rather than software firmware, thus reducing execution time while maintaining system compatibility
2Adaptability or versatility
If firmware is used to manage I/O operations, then the control logic can be updated and configured, but the firmware execution cannot be interleaved with I/O burst time of fast non-volatile memories like PRAM or MRAM
Solution Approach 1:
The patent replaces the firmware-based I/O management system with a hardware-based controller that processes I/O operations through dedicated hardware circuits. The controller includes a PCIe interface for host communication, an internal memory bus for data transfer, and hardware modules for command processing, data transfer, and completion handling, enabling parallel processing of I/O operations without firmware execution delays
Solution Approach 2:
The patent segments the I/O operation management into distinct hardware modules: a PCIe interface module for host communication, a command processing module for fetching and parsing commands, a data transfer module for moving data between host memory and non-volatile memory, and a completion handling module for managing operation completions. This segmentation enables concurrent execution of multiple I/O operations, significantly improving throughput for fast non-volatile memories
Data Source
AI summary
In a non-volatile memory controlling device, a first doorbell region is exposed to a configuration space of a host interface and updated when the host issues an input/output (I/O) request command to the host memory. A fetch managing module fetches the command from the host memory in response to an event signal generated when the first doorbell region is updated. A data transferring module checks a location of the host memory based on request information included in the command, and performs a transfer of target data for the I/O request between the host memory and the non-volatile memory module. A completion handling module writes a completion request in the host memory and handles an interrupt when the data transferring module completes to process the I/O request. A second doorbell region is exposed to the configuration space and updated when the I/O service is terminated by the host.