Embedding Hardware Objects in Event-Driven Simulators
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Solution Overview
Problem
Existing high-level modeling systems (HLMS) for electronic circuit design are limited in compatibility and functionality, as hardware objects created by tools like Xilinx System Generator are specific to the Simulink system and incompatible with other co-simulation frameworks, restricting the ability to perform co-simulation across different platforms.
Innovation Solution
The generation of an HDL proxy component with event handler functions and configuration bitstream allows for embedding hardware objects in event-driven simulators, enabling compatibility with various co-simulation frameworks by providing a generic interface for programmable logic circuits, and facilitating the creation of configuration parameters objects to manage port characteristics and bitstream locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware objects are created using Simulink-specific encapsulation and parameters, then the hardware objects can be efficiently simulated within the Simulink environment, but the hardware objects become incompatible with other co-simulation frameworks
Solution Approach 1:
The patent introduces an intermediary layer that translates between Simulink-specific hardware object interfaces and standard co-simulation frameworks. This mediator enables hardware objects to communicate effectively across different simulation platforms without losing efficiency or compatibility
Solution Approach 2:
The patent creates a universal hardware object interface that can function across multiple co-simulation frameworks simultaneously. By designing the hardware objects with multi-framework support, they maintain simulation efficiency while gaining versatility to work in different environments
2Ease of operation
If high-level abstractions are used in HLMS without explicit clock references, then the design process is simplified and more accessible, but the timing characteristics and precise correlation with implementation are lost
Solution Approach 1:
The patent performs preliminary timing analysis and clock synchronization setup during the high-level design phase. By pre-configuring timing characteristics in the abstract model, the system maintains design simplicity while ensuring accurate timing correlation with the final implementation
Solution Approach 2:
The patent implements feedback mechanisms that continuously verify timing characteristics between the high-level abstract model and the implementation. This feedback loop ensures that simplified designs maintain precise timing correlation without requiring explicit clock references in the high-level code
3Measurement precision
If detailed event-driven simulation is performed, then precise timing and behavior are captured, but the simulation time and computational resources increase significantly
Solution Approach 1:
The patent applies partial event-driven simulation by selectively applying detailed timing analysis only to critical paths and timing-sensitive portions of the design. Non-critical portions use simplified modeling, reducing overall simulation time while maintaining necessary timing precision where required
Data Source
AI summary
Various approaches for embedding a hardware object in an event-driven simulator are disclosed. The various approaches involve generating an HDL proxy component having an HDL definition of each port of the hardware object and respective event handler functions associated with input ports of the HDL proxy component. The event handler functions are responsive to simulation events appearing on the input ports. A configuration bitstream is generated for implementing the hardware object on a programmable logic circuit, and a first object is generated to contain configuration parameter values indicating characteristics of the ports and a location of the configuration bitstream. A second object is generated and is configured to initiate configuration of the programmable logic circuit with the configuration bitstream. The second object further provides input data to and receives output data from the programmable logic circuit.