Hardware Operating Windows for Safer Semiconductor Recipe Development
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Solution Overview
Problem
The complexity of semiconductor manufacturing processes and tool specifications leads to the risk of creating incorrect recipes that can damage wafers or tools, necessitating improved methods for generating and validating process recipes.
Innovation Solution
Implementing hardware operating window (HOW) analytics to generate a design of experiment (DoE) that incorporates prior data, physics-based models, and constraints to define a more accurate operational window, reducing the risk of hardware stability issues during recipe development.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If process engineers manually create recipes based on tool specifications and process requirements, then recipe development can be completed, but the complexity of hundreds of variables and tool specifications leads to incorrect recipes that may damage wafers or tools
Solution Approach 1:
The system performs preliminary actions by automatically generating candidate recipes and validating them against tool operating windows and process requirements before actual manufacturing. This includes running virtual simulations and checking constraints prior to physical implementation, preventing incorrect recipes from reaching production tools.
Solution Approach 2:
The system implements feedback loops where recipe candidates are evaluated against historical data, tool specifications, and process requirements. Invalid recipes are rejected and corrected through iterative optimization, with feedback from validation results continuously improving the recipe generation process.
2Manufacturing precision
If the allowable operating window for a tool is well-defined but complex, then tool operation constraints are established, but process engineers can still mistakenly create recipes that fall outside the defined operating window
Solution Approach 1:
The system replaces manual mechanical checking of operating windows with automated computational validation. Software algorithms automatically compare recipe parameters against defined operating windows, eliminating human error in determining whether recipes fall within acceptable ranges.
Solution Approach 2:
The system introduces an intermediary validation layer between recipe creation and tool execution. This intermediary automatically checks recipes against operating windows and provides certification before recipes are applied to production tools, serving as a safety buffer against errors.
3Productivity
If design of experiment (DoE) is used for generating new recipes, then process optimization can be achieved, but process runs may lead to damage to the tool and/or wafer if recipe conditions are significantly changed
Solution Approach 1:
The system applies preliminary anti-action by pre-validating all DoE recipe candidates against tool operating windows and damage thresholds before execution. The validation system proactively prevents harmful recipe conditions from being tested, countering potential damage before it occurs.
Solution Approach 2:
The system provides beforehand cushioning by establishing safety buffers and validation checks that protect against extreme or harmful recipe conditions. The system cushions against potential damage by rejecting recipes that would push tools or wafers beyond safe operating limits.
4Reliability
If margin testing is performed on recipe iterations, then recipe robustness can be verified, but additional time and resources are required for validation
Solution Approach 1:
The system performs preliminary margin validation through automated simulations and virtual testing before physical margin testing. This preliminary computational validation filters out weak recipes early, reducing the number of physical iterations needed and accelerating the overall validation process.
Data Source
AI summary
Embodiments disclosed herein include a method for use with a semiconductor processing tool. In an embodiment, the method comprises configuring the semiconductor processing tool, running a benchmark test on the semiconductor processing tool, providing hardware operating window (HOW) analytics, generating a design of experiment (DoE) using the HOW analytics, implementing process optimization, and releasing an iteration of the process recipe. In an embodiment, the method further comprises margin testing the iteration of the process recipe.