Hardware OS Timer Scheduler for Power-Efficient RTOS
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Solution Overview
Problem
Conventional RTOS timer schedulers are unreliable and prone to missing deadlines due to software-based implementation, leading to inefficiencies in timing control and power management, particularly in low power consumption modes.
Innovation Solution
A hardware-based OS timer is integrated with an ordinary timer to provide a system timer scheduler service, utilizing event-based design and timer alignment mechanisms to optimize both run-time and sleep mode power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If software-based scheduler timers are used, then the system is easier to implement, but the reliability and deadline guarantee deteriorate
Solution Approach 1:
The patent replaces software-based timer mechanisms with hardware-based timer circuits. The hardware timer generates interrupt signals directly from the system clock, eliminating the need for software polling and timing loops. This substitution of mechanical/hardware timing for software timing resolves the contradiction by providing reliable, deterministic timing intervals while maintaining ease of implementation through hardware automation.
Solution Approach 2:
The hardware timer automatically generates interrupt signals at precise time intervals without requiring continuous software intervention. The timer circuit self-manages the timing function by comparing the current clock count against a preset value and autonomously triggering interrupts, freeing the processor from timing management tasks while ensuring reliable deadline execution.
2Device complexity
If conventional scheduler timers are used, then the implementation is simpler, but interference between timers causes deadline misses
Solution Approach 1:
The patent segments the timing function into distinct hardware timer modules, each capable of independent operation with its own preset interval and interrupt output. This segmentation eliminates interference between timers by providing isolated timing circuits that do not share software resources or timing channels, ensuring that each timer can reliably meet its deadline independently of other timing operations.
3Speed
If the processor operates continuously, then timing control is more responsive, but power consumption increases
Solution Approach 1:
The hardware timer implements periodic interrupt generation based on predetermined time intervals derived from the system clock. This periodic action allows the processor to enter low-power sleep modes between interrupts, waking only when timing events occur. The responsive timing is maintained through the hardware timer's continuous clock counting, while power consumption is reduced by allowing the processor to remain idle during intervals between interrupts.
Data Source
AI summary
An apparatus for performing timer management regarding a system timer scheduler service includes: a processor arranged to control operations of the apparatus; an ordinary timer arranged to provide the processor with time ticks, for use of timing control; and a hardware-based Operating System (OS) timer arranged to provide the processor with at least one scheduler timer, for use of the system timer scheduler service. An associated method for performing timer management regarding a system timer scheduler service is also provided, and can be applied to the apparatus. In particular, the apparatus and the method can give considerations to both run-time power consumption and sleep mode power consumption. For example, the hardware-based OS timer can support an event-based OS timer scheduler to save the run-time power consumption. In another example, the hardware-based OS timer can support timer alignment in accordance with modulator/demodulator (modem) activities to minimize the sleep mode power consumption.