Hardware Packet Counting for High-Speed Network Tests
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Solution Overview
Problem
Conventional network speed test applications using processors with limited computing power face inefficiencies and resource constraints, particularly when employing UDP-based protocols, leading to underestimated network speeds and excessive resource consumption.
Innovation Solution
A network device and method that utilize hardware-based packet counting and proactive packet dropping to reduce processor load, allowing for efficient network speed testing in high-speed networks by offloading packet processing tasks to hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor with limited computing power is used to parse each UDP packet for network speed testing, then the network device can perform basic packet processing, but the processor resources and memory resources are excessively consumed, and the maximum measurable network speed is far lower than the actual network speed
Solution Approach 1:
The patent extracts the packet counting function from the processor and implements it in hardware (network interface card). The hardware counter automatically counts received packets without requiring processor intervention, thereby extracting the burden of packet processing from the limited-power processor while enabling accurate high-speed network measurement.
Solution Approach 2:
The patent introduces a hardware counter and proactive packet dropping circuit as intermediaries between the network interface and the processor. These hardware components mediate the packet processing by counting packets and selectively dropping them before the processor needs to handle them, reducing processor workload while maintaining measurement accuracy.
2Measurement precision
If the processor parses every received packet to ensure accurate counting, then the packet count accuracy is maintained, but the processor cannot keep up with high-speed networks and seriously underestimates the user's actual network speed
Solution Approach 1:
The patent extracts the packet counting function from the processor and implements it in hardware (network interface card). The hardware counter automatically counts received packets without requiring processor intervention, thereby extracting the burden of packet processing from the limited-power processor while enabling accurate high-speed network measurement.
Solution Approach 2:
The patent replaces the software-based packet processing mechanism with a hardware-based counting mechanism. The hardware counter in the network interface card provides a more powerful and faster mechanism for packet counting compared to software processing, enabling accurate measurement of high-speed networks.
3Reliability
If TCP protocol is used for network speed testing to ensure data transmission accuracy, then the reliability of data transmission is improved, but bandwidth bottlenecks occur and the network speed is seriously underestimated
Solution Approach 1:
The patent extracts the reliability assurance function from the TCP protocol layer and implements it through hardware mechanisms (counter and proactive packet dropping circuit). The hardware counter provides accurate packet counting without requiring TCP acknowledgment mechanisms, and the proactive packet dropping circuit controls packet flow to prevent buffer overflow, thereby maintaining reliability while eliminating TCP bandwidth bottlenecks.
Data Source
AI summary
A network device includes a network interface hardware circuit, a storage device, and a processor. The network interface hardware circuit receives packets from another network device. The network interface hardware circuit includes a counter and a proactive packet dropping circuit. The counter counts the packets during a period of network speed test, wherein the packets include first packets and second packets. The proactive packet dropping circuit proactively drops the second packets during the period of network speed test. The storage device stores a program code. The processor loads and executes the program code to perform the following operation: during the period of network speed test, reading packet count values of the counter that are generated at different time instants to calculate a number of received packets at the network device within a time interval between the different time instants.