Hardware Packet Editor Offloads CPU Cycles for Gateway Throughput

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Solution Overview

Problem

Current service gateways face high computational and memory access costs when modifying data packets, as this process is typically handled by processor modules, leading to resource constraints for handling additional packets or sessions.

Innovation Solution

A hardware-based packet editor is introduced to offload data packet modification, utilizing a packet editing script to identify and apply modifications, such as copying data blocks into a packet buffer, and generating a modified packet, thereby reducing the processor's workload.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data packet modification is performed by a processor module, then the service gateway can analyze and modify packets, but the processor consumes excessive CPU cycles and memory access bandwidth

Engineering Contradiction:
Improvepacket modification throughputVSAvoidCPU cycle consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent replaces the software-based packet modification process (mechanical system) with a hardware-based packet editor that performs the same function using dedicated hardware circuits. This substitution eliminates the need for CPU intervention in packet modification operations, thereby reducing CPU cycle consumption while maintaining or improving modification throughput.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent extracts the packet modification function from the general-purpose processor module and implements it as a separate, dedicated hardware-based packet editor. This extraction allows the processor to focus on higher-level tasks while the hardware module handles the computationally intensive packet modification operations independently.

Inventive Principle:
Principle #2Taking out (Extraction)

2Adaptability or versatility

If data packet modification is performed by a processor module, then packets can be modified according to analysis results, but the processor resources are constrained for handling additional packets or sessions

Engineering Contradiction:
Improveservice gateway capacityVSAvoidprocessor throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent extracts the packet modification function from the general-purpose processor module and implements it as a separate, dedicated hardware-based packet editor. This extraction allows the processor to focus on higher-level tasks while the hardware module handles the computationally intensive packet modification operations independently, thereby increasing overall service gateway capacity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the service gateway into distinct functional modules: a processor module for analysis and control, and a hardware-based packet editor for execution of modifications. This segmentation allows parallel operation of different functions, improving the gateway's ability to handle multiple packets and sessions simultaneously.

Inventive Principle:
Principle #1Segmentation

3Productivity

If a hardware-based packet editor is introduced, then processor resources are freed for additional tasks, but the device complexity increases

Engineering Contradiction:
Improveprocessor availabilityVSAvoidservice gateway architecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces software-based packet modification with a hardware-based packet editor, which虽然increases hardware complexity but eliminates the need for complex software processing and memory management for packet modification, thereby simplifying the overall system architecture in terms of software requirements.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces a programmable interface between the processor module and the hardware-based packet editor, allowing the processor to configure and control the hardware module through scripts. This intermediary interface provides flexibility while maintaining clear separation of concerns, managing the complexity through standardized communication protocols.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10069946B2Hardware-based packet editor
Publication Date: 2018.09.04 A10 NETWORKS INC
  • US10069946B2 patent drawing
  • US10069946B2 patent drawing
  • US10069946B2 patent drawing

AI summary

Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.