Hardware-Accelerated Packet Generation for Network Speed Tests
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Solution Overview
Problem
Conventional network speed test applications using processors with limited computing power face resource bottlenecks and underestimate actual network speeds due to the processor's inability to generate enough packets efficiently for high-speed network tests.
Innovation Solution
Offload the packet generation task from the processor to a hardware acceleration circuit, which self-generates packets based on transmission parameters calculated by the processor, using hardware-accelerated packet processing to meet the requirements of high-speed network tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor generates UDP packets for upload speed test, then the network speed test can be performed, but the processor consumes excessive computing resources and memory resources
Solution Approach 1:
The patent extracts the packet generation function from the processor and implements it in the network card's hardware. The processor only needs to initiate the speed test and receive results, while the network card independently generates and sends test packets, significantly reducing processor resource consumption.
Solution Approach 2:
The network card acts as an intermediary between the processor and the network. It receives test parameters from the processor, generates packets locally using its own resources, and reports results back, eliminating the need for the processor to directly generate each packet.
2Measurement precision
If the processor with limited computing power generates packets for high-speed network test, then the test can proceed, but the maximum measurable network speed is far lower than the actual network speed
Solution Approach 1:
The packet generation function is extracted from the processor and implemented in the network card's hardware. This allows the network card to generate packets at line rate without being constrained by the processor's computing power, enabling accurate measurement of high-speed networks.
Solution Approach 2:
The software-based packet generation on the processor is replaced with hardware-based packet generation in the network card. This substitution enables packet generation rates that match high-speed network interfaces, eliminating the bottleneck that previously limited measurement accuracy.
3Productivity
If the processor occupies all working time for packet generation, then more packets can be generated, but the processor's limited computing power still prevents meeting high-speed network test requirements
Solution Approach 1:
The computationally intensive packet generation task is extracted from the processor and assigned to the network card's hardware. This allows the processor to maintain low power consumption while the network card handles the high-throughput packet generation required for high-speed network testing.
Solution Approach 2:
The network card creates local copies of packet templates and generates actual packets in hardware without requiring the processor to generate each packet individually. This copying approach enables high throughput while minimizing processor involvement and power consumption.
Data Source
AI summary
A network device includes a storage device, a processor and a hardware acceleration circuit. The storage device is arranged to store program codes. The processor is arranged to load and execute the program codes to perform the following operation: during a network speed test period, calculating at least one transmission parameter. The hardware acceleration circuit is arranged to provide a function of hardware-accelerated packet processing, wherein during the network speed test period, the hardware acceleration circuit is further arranged to refer to the at least one transmission parameter to self-generate a plurality of packets and send the plurality of packets to another network device for network speed test.