Hardware Parser for LL(1) Grammar Validation
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Solution Overview
Problem
Existing approaches to parsing data against a grammar that defines a data format to validate the data before subsequent processing are vulnerable to security risks, as they rely on general-purpose computers that can execute arbitrary code, potentially leading to false parsing and security breaches.
Innovation Solution
A hardware description is generated to configure a digital electronic circuit, such as an ASIC or FPGA, to parse input data against an LL(1) grammar by implementing a recursive transition network (RTN) or augmented transition network (ATN) within the circuit, thereby reducing the risk of executing malicious code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general-purpose computers are used for parsing data against a grammar, then parsing flexibility and adaptability are improved, but security reliability deteriorates due to vulnerability to malicious code execution
Solution Approach 1:
The patent replaces the software-based parsing system (mechanical system) running on general-purpose computers with a hardware-based digital electronic circuit implementation. This substitution eliminates the ability to execute arbitrary code while maintaining parsing functionality through dedicated hardware logic that implements the grammar rules directly in circuitry, thus resolving the security vulnerability while preserving adaptability through configurable hardware designs.
2Reliability
If a hardware-based parser is implemented to improve security, then security reliability is improved, but device complexity increases due to custom circuit design
Solution Approach 1:
The patent segments the parsing functionality into modular components represented by the grammar rules (e.g., start symbol, production rules, non-terminals). Each grammar rule can be implemented as a separate modular circuit block, allowing the complex parsing task to be divided into manageable, independently designable units. This segmentation reduces overall circuit complexity by enabling systematic design and verification of individual components.
Solution Approach 2:
The patent creates a universal hardware parser that can parse multiple different grammars and data formats through configurable hardware logic. Instead of designing separate dedicated circuits for each grammar, the system uses a general-purpose hardware parsing engine that can be configured to implement different LL(1) grammars, thereby reducing device complexity through reuse and standardization while maintaining security benefits.
3Adaptability or versatility
If software parsing is used to handle arbitrary context-free grammars, then adaptability is improved, but harmful factors increase due to potential code execution vulnerabilities
Solution Approach 1:
The patent replaces software-based grammar parsing with hardware-based parsing logic. The digital electronic circuit is configured to implement the grammar rules directly in hardware, eliminating the ability of malicious input data to trigger arbitrary code execution while maintaining the capability to parse arbitrary context-free grammars through configurable hardware design. This substitution fundamentally removes the security vulnerability class associated with software parsers.
Data Source
AI summary
Generating a hardware description for configuring a digital electronic circuit, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA), wherein the hardware description configures the digital electronic circuit to parse input data comprising a sequence of input tokens against an LL (1) grammar. This is achieved by implementing a recursive transition network (RTN) or an augmented transition network (ATN) representing the grammar within the digital electronic circuit. When the grammar defines a data format, such as a JSON schema, XML Schema Definition (XSD), or ASN.1 schema, a document can be validated against the data format by the configured digital electronic circuit processing the document as the input data.