Network Interface Hardware Pipeline With Programmable Core Offload
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Solution Overview
Problem
Network devices relying heavily on programmable cores for packet processing suffer from reduced data transfer speed and throughput due to software running slower than hardware, leading to performance issues and inflexibility.
Innovation Solution
Integrating a hardware pipeline tightly with programmable operations, allowing programmable cores to access hardware parser results and steering metadata, and enabling selective hardware pipeline operations to accelerate computation and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If programmable cores are used to provide packet processing capability, then flexibility and intelligence are improved, but data transfer speed and throughput decrease
Solution Approach 1:
The system segments packet processing into two distinct paths: a hardware pipeline for high-speed standard packet processing and a programmable core for complex intelligent tasks. This segmentation allows each component to operate in its optimal performance zone, with the hardware pipeline handling routine traffic at line rate and the programmable core processing only when needed.
Solution Approach 2:
The patent merges the hardware pipeline and programmable core into a unified network interface device with shared memory and coordinated control. The hardware pipeline includes a parser engine and flow data structure engine that can offload specific processing tasks to the programmable core, creating a hybrid architecture that combines the speed of hardware with the flexibility of software.
2Adaptability or versatility
If programmable cores are used for intelligent tasks, then processing capability is improved, but throughput decreases
Solution Approach 1:
The hardware pipeline performs preliminary packet parsing and classification before tasks are assigned to the programmable core. The parser engine pre-processes incoming packets to extract relevant information, and the flow data structure engine pre-establishes matching rules, so that when the programmable core needs to intervene, the work is already partially completed, reducing its processing burden and maintaining high throughput.
3Adaptability or versatility
If software-based packet processing is used, then programmability is improved, but initialization time increases
Solution Approach 1:
Flow data structures are pre-configured in the hardware pipeline before runtime operation. The hardware pipeline can be quickly programmed by loading flow data structures into its dedicated memory, which is much faster than software initialization. This preliminary configuration of processing rules in hardware form allows the system to achieve programmability with minimal initialization overhead.
Data Source
AI summary
A network device includes a programmable core and a hardware pipeline having a parser engine to parse and retrieve information from a network packet and a set of hardware engines coupled to the parser engine. The set of hardware engines is to determine a packet-processing action to be performed based on the retrieved information and send an action request to the programmable core to trigger the programmable core to execute a hardware thread to perform a job. The job is associated with the packet-processing action and generates contextual data. The set of hardware engines retrieves and integrates the contextual data into performing the packet-processing action.