Hardware Pipeline Partitioning to Eliminate Task Idle Time
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Solution Overview
Problem
Conventional processors experience inefficiencies due to 'spin-up' and 'spin-down' periods when processing tasks with different configurations or data dependencies, leading to idle times and reduced pipeline efficiency.
Innovation Solution
The processor is partitioned into upstream and downstream sections with a blocking circuit to allow independent configuration and data processing, enabling overlapping of task spin-up with current task processing and spin-down with next task processing, and utilizing multiple buffered configuration registers to reduce idle times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor uses a single hardware pipeline for task processing, then the device complexity is reduced, but the pipeline efficiency decreases due to spin-up and spin-down idle times when processing tasks with different configurations
Solution Approach 1:
The hardware pipeline is divided into an upstream section and a downstream section with a blocking circuit between them. This segmentation allows independent configuration of each section, enabling the upstream section to prepare for the next task while the downstream section completes the current task, thereby eliminating spin-up and spin-down idle times and improving pipeline efficiency without requiring complete pipeline reconfiguration
Solution Approach 2:
The upstream section of the pipeline can be configured in advance for the next task while the downstream section is still processing the current task. This preliminary configuration action eliminates the traditional spin-up idle time by having the upstream section ready to process data as soon as the downstream section becomes available, maintaining continuous pipeline operation
2Productivity
If the processor waits for the current task to complete before starting the next task, then configuration conflicts are avoided, but the loss of time increases due to idle periods
Solution Approach 1:
Dividing the pipeline into upstream and downstream sections with a blocking circuit enables overlapping of task preparation and execution. The upstream section can be configured for the next task during the downstream section's processing of the current task, eliminating idle time between tasks while maintaining configuration integrity through the blocking circuit
Solution Approach 2:
The blocking circuit maintains continuous useful action by allowing the upstream section to continuously prepare for the next task without interruption. When the downstream section finishes processing, the blocking circuit opens to allow the pre-configured upstream section to immediately feed data to the downstream section, eliminating idle periods and maintaining continuous productive operation
Data Source
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Figure 3~4
Figure 3a
AI summary
A processor comprising a blocking circuit between an upstream section and a downstream section of a hardware pipeline; and control circuitry which triggers the upstream section to process an upstream phase of a first task, with the blocking circuit in an open state whereby first data from the processing of the upstream phase of the first task passes through from the upstream section to be processed in a downstream phase of the first task. In response to detecting that the upstream section has finished processing the upstream phase of the first task, the control circuitry triggers the upstream section to start processing a second task while the downstream section is still processing the downstream phase of the first task, and switches the blocking circuit to a closed state blocking second data from the processing of the upstream phase of the second task passing to the downstream section.