Hardware PLL Switching for SoC Clock and Power Management
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Solution Overview
Problem
Managing multiple phase lock loops (PLLs) on a system-on-a-chip (SOC) is complex due to increased integration, leading to burdensome tasks such as switching core clocks, managing power states, and reconfiguring PLLs, which hampers energy efficiency and flexibility in power management.
Innovation Solution
A hardware phase lock loop (PLL) switching control block is introduced, coupled with a software interface, to efficiently search for and switch between PLLs, disconnecting core clocks from current PLLs and reconnecting them to target PLLs, thereby reducing the number of active PLLs and enhancing energy management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PLLs are integrated on an SOC to support increased integration and multiple clock sources, then clock source versatility and processing performance are improved, but system complexity and difficulty of managing PLL switching increase
Solution Approach 1:
A hardware controller is introduced as an intermediary between the software interface and the PLLs. The controller receives requests from software, automatically searches for suitable target PLLs based on specified conditions, and executes the switching process. This mediator handles the complex coordination of disconnecting clocks from current PLLs, reconnecting to target PLLs, and managing relocking sequences, thereby reducing software burden while maintaining versatility.
Solution Approach 2:
The hardware controller autonomously performs the PLL search and switching operations without requiring detailed software intervention. When software provides a search request with conditions, the controller independently evaluates available PLLs, selects appropriate targets, and executes the switching sequence. This self-service capability automates the management of multiple PLLs while preserving the versatility of having multiple clock sources available.
2Adaptability or versatility
If software manually manages PLL switching and reconfiguration, then flexibility in power management policies is maintained, but processing time and energy consumption increase
Solution Approach 1:
The manual software-based PLL management process is replaced with a hardware-controlled automated system. The hardware controller executes switching operations through dedicated control logic and circuitry, significantly reducing the time required for PLL search, selection, and switching compared to software instruction execution. This mechanical/electrical substitution maintains power management flexibility through software interfaces while dramatically reducing switching time.
Solution Approach 2:
The hardware controller maintains readiness to execute PLL switching operations by continuously monitoring system state and pre-configuring control pathways. When a switching request is received, the controller can rapidly evaluate available PLLs and initiate the switching sequence without the delays associated with software processing. This preliminary preparation capability reduces the effective switching time while preserving flexible power management through software-initiated requests.
3Productivity
If more PLLs are kept active to provide clock sources for multiple cores, then system performance and responsiveness are improved, but energy consumption increases
Solution Approach 1:
The system dynamically adjusts the number of active PLLs based on real-time performance requirements and power management policies. The hardware controller can rapidly switch between different PLL configurations, enabling the system to activate additional PLLs when high performance is needed and consolidate to fewer active PLLs when power savings are prioritized. This dynamic adaptability allows the system to optimize the trade-off between productivity and energy consumption.
Solution Approach 2:
The system changes operational parameters by switching clock sources between different PLLs based on power and performance requirements. The hardware controller can reconfigure which PLLs are active and which clocks they provide, allowing the system to consolidate workloads onto fewer active PLLs to reduce energy consumption while maintaining the capability to activate additional PLLs when performance demands increase. This parameter changing capability enables flexible optimization of the performance-energy trade-off.
Data Source
AI summary
A system and method for efficiently managing multiple PLLs on a system on a chip (SOC). A SOC includes a hardware phase lock loop (PLL) switching control block coupled to a software interface. The hardware PLL switching (HPS) control block receives PLL switch requests from software. The request identifies a given core clock received by a given processing core of multiple processor cores on the SOC and indicates the identified core clock is not to be provided anymore by a current PLL. The request indicates a given search method including search conditions. The HPS control block searches for a target PLL that satisfies these search conditions. In response to finding the target PLL, the HPS control block changes clock network connections and parameters across the die of the SOC. These changes across the die disconnect the identified core clock from the current PLL and connects the identified core clock to the target PLL.