Hardware Polling Unit Reduces Processor Load
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Solution Overview
Problem
Polling in computer systems imposes a heavy processing load on processors due to frequent, unnecessary register checks, reducing efficiency and requiring frequent bus access, which can lead to reduced processing speed and increased power consumption.
Innovation Solution
A computer system design that incorporates a polling unit to perform periodic data checks and generate interrupt signals when conditions are met, allowing the processor to focus on other tasks and reducing its processing burden, with a bus controller prioritizing processor access to maintain processing speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polling is performed by firmware in the processor, then the processor can monitor register contents periodically, but the processing load on the processor increases significantly
Solution Approach 1:
The polling function is extracted from the processor firmware and implemented as a separate hardware polling unit. This polling unit independently monitors register contents and generates interrupt signals when conditions are met, thereby removing the continuous polling burden from the processor while maintaining reliable monitoring capability.
Solution Approach 2:
A hardware polling unit is introduced as an intermediary component between the processor and the monitored registers. This intermediary handles the periodic monitoring and conditional branch generation, allowing the processor to focus on primary processing tasks while the polling unit manages monitoring operations.
2Reliability
If the processor periodically reads register contents during polling, then status monitoring is achieved, but most reads are wasted accesses that reduce processing efficiency
Solution Approach 1:
The polling unit autonomously performs the polling operation by automatically reading register contents at predetermined intervals and evaluating conditions without requiring processor intervention. This self-service mechanism eliminates wasted processor cycles while ensuring continuous status monitoring.
Solution Approach 2:
The polling unit implements periodic reading of register contents at predetermined intervals, performing monitoring only when necessary rather than continuously. This periodic action reduces the number of wasted accesses while maintaining effective status monitoring capability.
3Reliability
If the polling unit accesses the address space frequently, then polling conditions can be checked, but bus access conflicts increase and processor speed decreases
Solution Approach 1:
The bus controller acts as an intermediary that manages access conflicts between the polling unit and processor. It detects when both entities request bus access simultaneously and resolves the conflict by prioritizing processor access, thereby preventing speed degradation while allowing the polling unit to maintain accurate monitoring.
Solution Approach 2:
The bus access priority is dynamically adjusted based on the operational state of the processor and polling unit. When the processor requires high-speed access, the bus controller temporarily reduces polling unit access frequency, creating a dynamic balance that maintains both polling accuracy and processor speed.
Data Source
AI summary
A computer system is provided that can realize polling without increasing the processing burden on the processor. Data is read by a polling unit during a prescribed period from a prescribed address in the address space. Then, if the read data satisfies a prescribed condition, an interrupt signal is generated in the polling unit. Since processor can receive the interrupt from hardware instead of performing polling with firmware, the processing burden on processor 10 can be significantly reduced.