Hardware Power Estimator With Nonlinear Scaling for Rapid Analysis
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Solution Overview
Problem
Current methods for estimating power consumption in microcontrollers and ASICs are complex and time-consuming, requiring gate-level simulations or current measurements, which are impractical for quick power-performance optimization, especially in systems with numerous configurations and dynamic power variations.
Innovation Solution
A hardware power estimator (HPE) using a scaling circuit and multiply-add (MADD) circuit arrangement to estimate power consumption in real-time by applying activation functions to input data representing the state or activity of IP blocks, reducing computational complexity through hardware-based estimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gate-level simulations or timing-based activity simulations are used to estimate power consumption, then measurement precision is improved, but productivity deteriorates due to long simulation times and complexity
Solution Approach 1:
The patent creates a simplified hardware power estimator model that copies the essential power consumption characteristics of the microcontroller without requiring full gate-level simulation. This model uses configurable parameters representing different microcontroller components and their power states, enabling fast power estimation while maintaining reasonable accuracy for optimization purposes
Solution Approach 2:
The invention employs a lightweight power estimation model that is computationally inexpensive and can be rapidly evaluated multiple times during design optimization. Rather than using expensive, time-consuming gate-level simulations, the model provides sufficient accuracy for iterative optimization with minimal computational resources
2Measurement precision
If the hardware power estimator uses more complex models to improve accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The power estimator is segmented into multiple independent configurable parameters, each representing a specific microcontroller component or power state. This segmentation allows the model to capture complex power consumption patterns through simple parameter combinations rather than requiring a complex monolithic model
Solution Approach 2:
The invention uses configurable parameters to represent different microcontroller configurations, power states, and operational modes. By changing these parameters, the estimator can adapt to various scenarios without requiring structural changes to the estimator itself, maintaining simplicity while achieving accuracy across diverse conditions
Data Source
AI summary
A hardware power estimator (HPE) configured to provide a power estimate for an electronic device includes a scaling circuit configured to receive an input and to generate a scaled non-linear output of the input includes the scaling circuit applying an approximation of an activation function to the input. The HPE further includes a multiply-add (MADD) circuit arrangement configured to generate an output indicating a mathematical power estimation of the electronic device using the output of the scaling. Input to the scaling circuit includes data values representing state information or activity information of one or more components or Intellectual Property (IP) blocks of the electronic device.