Hardware Predictor for Cache Line Demotion in NFV Data Transfers
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Solution Overview
Problem
Current network infrastructure faces performance bottlenecks in inter-VM data transfer due to software and hardware inefficiencies, particularly in packet throughput for small packets, which is critical for telecommunication companies, leading to unsatisfactory results despite high bandwidth capabilities.
Innovation Solution
Implementing a hardware predictor that optimizes intra-VM data transfer by using a Cache Line LLC Allocation (CLLA) instruction to proactively allocate cache lines into the Last Level Cache (LLC), reducing memory reference latency and coherence messages, and employing a hardware predictor to adaptively enable or disable CLLA based on access patterns to minimize performance inversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If cache line demotion instruction (CLLA) is used to proactively allocate cache lines into LLC, then memory reference latency is reduced and throughput is increased, but performance inversion occurs when both producer and consumer threads reside on the same physical core
Solution Approach 1:
The patent implements preliminary action by using the CLLA instruction to proactively allocate cache lines into the LLC before they are actually needed by consumer threads. This advance preparation reduces memory reference latency when consumer threads need to access the cache lines, as the data is already positioned in the optimal cache location rather than requiring a slow memory fetch at the moment of need.
Solution Approach 2:
The patent employs feedback through a hardware predictor that monitors cache access patterns and dynamically determines whether to enable or disable the CLLA instruction. The predictor analyzes whether cache lines are more likely to be accessed by local threads (same core) or remote threads (different cores), and adjusts CLLA behavior accordingly. This feedback mechanism prevents performance inversion by disabling CLLA when local thread access is detected, while enabling it when remote access is predicted, thus optimizing throughput for different workload scenarios.
2Use of energy by moving object
If CLLA instruction is enabled to reduce coherence messages, then energy consumption is reduced, but cache resource utilization efficiency decreases due to performance inversions
Solution Approach 1:
The patent applies dynamics by making the CLLA instruction behavior adaptive rather than static. The hardware predictor continuously monitors cache access patterns and dynamically adjusts whether CLLA is enabled or disabled based on real-time workload characteristics. This dynamic adaptation allows the system to optimize for energy savings when remote access is detected while maintaining cache resource utilization efficiency when local access is predicted, thus resolving the contradiction between energy consumption and adaptability.
Data Source
AI summary
Apparatus and methods implementing a hardware predictor for reducing performance inversions caused by intra-core data transfer during inter-core data transfer optimization for network function virtualizations (NFVs) and other producer-consumer workloads. An apparatus embodiment includes a plurality of hardware processor cores each including a first cache, a second cache shared by the plurality of hardware processor cores, and a predictor circuit to track the number of inter-core versus intra-core accesses to a plurality of monitored cache lines in the first cache and control enablement of a cache line demotion instruction, such as a cache line LLC allocation (CLLA) instruction, based upon the tracked accesses. An execution of the cache line demotion instruction by one of the plurality of hardware processor cores causes a plurality of unmonitored cache lines in the first cache to be moved to the second cache, such as from L1 or L2 caches to a shared L3 or last level cache (LLC).