Hardware Processing Function in Hierarchical Memory for Cache Coherence
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Solution Overview
Problem
Microprocessor systems face inefficiencies due to cache incoherency and cache pollution, particularly when using hardware accelerators, which can disrupt the effectiveness of hierarchical memory systems and burden the processor with synchronization and control issues.
Innovation Solution
The integration of a Hardware Processing Function (HPF) within a hierarchical memory system, allowing data manipulation operations to be performed without introducing cache incoherency or pollution, by attaching the HPF to the memory system rather than the processor core, and using a Memory Instruction (MEMI) to manage cache hierarchy refill policies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware accelerators are used to perform data manipulations, then processing capability is improved, but cache incoherency and cache pollution occur
Solution Approach 1:
The patent introduces a memory system intermediary between the processor core and hardware accelerators. This intermediary manages cache coherence by intercepting memory accesses from hardware accelerators and coordinating them with cache lines, thereby enabling hardware acceleration while preventing cache pollution and incoherency.
Solution Approach 2:
The patent segments the memory hierarchy into distinct levels (L1 cache, L2 cache, main memory) with specific roles. Hardware accelerators access memory through this segmented hierarchy, and the system manages coherence by treating different memory levels as separate coherence domains, allowing acceleration without compromising overall cache consistency.
2Speed
If hardware accelerators perform memory accesses, then data manipulation speed is improved, but cache access latency increases
Solution Approach 1:
The patent implements preliminary actions by pre-loading frequently accessed data into appropriate cache levels before hardware accelerators need it. The memory system proactively manages cache refill policies to ensure that data required by hardware accelerators is already in optimal cache locations, reducing access latency when acceleration operations commence.
3Adaptability or versatility
If multiple devices access various system memory levels, then system functionality is improved, but cache incoherency occurs
Solution Approach 1:
The patent implements feedback mechanisms where the memory system continuously monitors access patterns and coherence status across multiple devices. When incoherency is detected, the system automatically initiates coherence restoration operations, allowing multiple devices to access memory simultaneously while maintaining consistency through active feedback-based coordination.
Data Source
AI summary
Apparatus and method for employing a Hardware Processing Function in a processor system using a hierarchical memory. Embodiments of the disclosed invention may be used to enhance processor performance and functionality while maintaining cache coherency and reducing cache pollution. A system includes a processor, a hierarchical memory system coupled to the processor, and a Hardware Processing Function coupled to the hierarchical memory system. The processor is configured to decode an instruction and the hierarchical memory system is configured to execute the instruction. The instruction directs the memory system to perform a data manipulation. The processor transfers a value to the memory system. The value comprises a location of source data to be manipulated, a selection of a Hardware Processing Function to perform the data manipulation, and a destination storage location where the manipulated data is to be stored.