Hardware Protocol Engine for Fast, Flexible Capability Exchange
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Solution Overview
Problem
Current interconnection interface technologies in mobile devices face challenges in achieving high transmission speeds, low power consumption, expandability, and ease of adoption, particularly in systems adhering to standards like UFS, where efficient preparation of capability information for link establishment is lacking.
Innovation Solution
A controller is designed with a hardware protocol engine and processing unit to perform capability extraction and frame formatting, enabling efficient and flexible preparation of capability information during the Link Startup Sequence (LSS) for interconnection protocols, allowing for seamless link establishment between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If capability information preparation is performed using traditional software-based methods, then flexibility in adapting to protocol updates is improved, but transmission speed and processing efficiency deteriorate
Solution Approach 1:
The capability information preparation process is divided into two independent segments: hardware-based capability extraction and frame formatting, and software-based capability information generation. This segmentation allows the hardware to handle speed-critical operations while software handles flexibility-critical operations, resolving the contradiction between transmission speed and adaptability.
Solution Approach 2:
A hardware protocol engine acts as an intermediary between the physical layer and the processing unit. It receives capability information from the processing unit, performs hardware-based extraction and formatting, and transmits the formatted capability frames to the second device. This intermediary enables parallel processing of speed-critical and flexibility-critical functions.
2Productivity
If hardware protocol engine performs all capability information preparation, then transmission efficiency is improved, but adaptability to protocol updates deteriorates
Solution Approach 1:
The system segments the capability information preparation into hardware-based extraction/formatting (for efficiency) and software-based generation (for adaptability). The processing unit generates capability information according to the latest protocol specifications, while the hardware protocol engine efficiently extracts and formats this information for transmission.
Solution Approach 2:
The hardware protocol engine is designed with universal functionality to support multiple protocol versions. It can process capability information generated according to different protocol specifications (UniPro 1.8, 2.0, and future versions) through the same hardware extraction and formatting mechanisms, maintaining adaptability while preserving transmission efficiency.
3Measurement precision
If capability information is prepared using detailed software processing, then accuracy and completeness of capability data is improved, but power consumption increases
Solution Approach 1:
The system extracts the power-intensive capability extraction and frame formatting operations from the software domain and places them in the hardware domain. The hardware protocol engine performs these operations using dedicated circuits, significantly reducing power consumption while maintaining the accuracy and completeness of capability information through verified hardware logic.
4Adaptability or versatility
If traditional link establishment processes are used, then compatibility with existing systems is maintained, but link establishment time increases
Solution Approach 1:
The hardware protocol engine performs capability extraction and frame formatting in advance during the Link Startup Sequence, before actual data transmission begins. This preliminary hardware-based preparation reduces the time required for link establishment while maintaining compatibility with existing UniPro protocol requirements and system architectures.
Data Source
AI summary
A controller capable of preparing capability information for an interconnection protocol and an electronic device are provided. The controller is for a first device linkable to a second device according to the interconnection protocol. The controller includes a hardware protocol engine and a processing unit. The hardware protocol engine is for implementing a link layer of the interconnection protocol, and capable of performing capability extraction and frame formatting to output capability frame information to a data buffer region and capable of sending, according to content of the data buffer region, a capability frame to the second device during Link Startup Sequence (LSS) capability exchange for the interconnection protocol. The processing unit is configured to be capable of modifying, during the LSS capability exchange, the content of the data buffer region after the capability frame information is output to the data buffer region and before the capability frame is sent to the second device.