Hardware PWM Generation Circuit for CPU-Free Motor Speed Control
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Solution Overview
Problem
Existing PWM circuits in industrial automation and motor control systems require complex software control and resource-intensive frequency division operations, which can lead to inefficiencies and increased complexity.
Innovation Solution
A PWM generation circuit with a second clock prescaler and a PWM signal generator, along with a PWM sampling and detection module, that includes a filter, step counting sub-module, and speed detector, allowing for adjustable frequency division and reduced software involvement in controlling motor systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If PWM circuits are implemented by peripheral devices such as square-wave oscillators or single-limit comparators with CPU time sequence control, then the PWM generation functionality is achieved, but the software interrupt process becomes complex and software resources are wasted
Solution Approach 1:
The PWM generation circuit is implemented as a self-contained hardware module that autonomously generates PWM signals without requiring CPU intervention. The circuit includes internal frequency dividers, counters, and comparators that automatically produce the PWM output based on preset parameters, eliminating the need for complex software interrupt handling and CPU time sequence control.
Solution Approach 2:
The patent replaces software-based PWM generation with a hardware-based circuit implementation. The mechanical/software control system is substituted with an electronic hardware circuit that uses clock signals, frequency dividers, and voltage comparators to generate PWM signals, thereby reducing software resource consumption and improving real-time performance.
2Adaptability or versatility
If frequency division operations are performed through software in existing PWM circuits, then the PWM signal frequency can be adjusted, but software resources are consumed and control efficiency is reduced
Solution Approach 1:
The patent replaces software-based frequency division with hardware frequency divider circuits. These circuits use clock signals and counter mechanisms to automatically divide the input frequency and generate the desired PWM output frequency, eliminating the need for software intervention and improving control efficiency while maintaining frequency adjustability through hardware parameter settings.
Solution Approach 2:
The frequency division ratio is made dynamically adjustable through hardware configuration rather than fixed software settings. The circuit can adapt to different frequency requirements by changing hardware parameters such as prescaler values or clock division ratios, providing versatility without consuming software resources.
3Reliability
If CPU is involved in frequency division operations for PWM generation, then the PWM signal can be generated, but the software complexity increases and motor control efficiency decreases
Solution Approach 1:
The patent extracts the frequency division and PWM generation functions from the CPU control system and implements them as a dedicated hardware circuit. This separates the PWM generation task from the main CPU operations, allowing the CPU to focus on higher-level control tasks while the hardware circuit handles the low-level signal generation autonomously.
Solution Approach 2:
The PWM generation circuit is designed to be self-sufficient, with internal frequency dividers, counters, and comparators that automatically perform all necessary operations to generate the PWM signal. The circuit does not require CPU involvement in frequency division or signal generation, thereby reducing software complexity and improving motor control efficiency.
Data Source
AI summary
Disclosed are a Pulse Width Modulation (PWM) generation circuit, a processing circuit and a chip. The PWM generation circuit is used for controlling a rotation speed of an external motor system. The PWM generation circuit includes a second clock prescaler and a PWM signal generator. A frequency division output end of the second clock prescaler is connected to a data input end of the PWM signal generator. The PWM signal generator includes an output frequency divider and a comparator. A clock output end of the output frequency divider is connected to a comparison input end of the comparator. By means of the technical solution, PWM signals with different duty ratios.