Hardware Queue Scheduler for Packet-Based System Stimulator
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Solution Overview
Problem
Current methods for testing packet-based systems lack flexibility in controlling data packet generation, particularly in handling real-time intervals, interleaved packets, and special packet types, which are essential for protocols like DigRF V3.07, and do not allow for sufficient control over variables such as time-between-packets, looping, and wait states.
Innovation Solution
A stimulator apparatus with hardware-based queue schedulers and a priority scheduler that generates and schedules data packets based on timing requirements and priorities, allowing for real-time transmission and coordination across multiple buses, enabling the generation of data packets with varying methodologies and purposes, and accommodating different timing and dependency requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional testing methods are used for packet-based systems, then basic system operation can be verified, but flexibility in controlling data packet generation is insufficient
Solution Approach 1:
The system divides packet generation control into multiple independent hardware-based queue schedulers, each managing specific packet types or timing requirements. This segmentation allows flexible control of different packet streams while keeping each scheduler's complexity manageable and modular.
Solution Approach 2:
The patent implements dynamically configurable queue schedulers that can adjust packet generation parameters in real-time based on timing requirements and system state. The hardware-based schedulers respond dynamically to changing conditions, enabling adaptable packet generation without requiring complete system redesign.
2Reliability
If real-time packet transmission is implemented, then protocol compliance (e.g., DigRF V3.07) is achieved, but control over timing variables becomes more difficult
Solution Approach 1:
The hardware-based queue schedulers autonomously manage timing variables and packet transmission schedules without requiring complex external control. Each scheduler independently handles its assigned packet types, automatically adjusting to timing requirements and reducing the operational burden on external controllers.
Solution Approach 2:
The patent replaces software-based timing control with hardware-based queue schedulers that directly manage packet transmission timing. This substitution provides more precise and reliable timing control while simplifying the operational interface, as hardware circuits naturally enforce timing constraints without complex software management.
3Adaptability or versatility
If multiple packet types with different timing requirements are generated, then comprehensive system testing is enabled, but coordination across multiple buses becomes more complex
Solution Approach 1:
The system assigns different hardware-based queue schedulers to different buses and packet types, segmenting the coordination task into manageable independent units. Each scheduler handles specific packet streams for specific buses, reducing overall coordination complexity while enabling comprehensive multi-bus testing.
Solution Approach 2:
The hardware-based queue schedulers are designed with universal functionality to handle multiple packet types and interface with different buses using the same underlying mechanism. This multi-functionality reduces coordination complexity by providing a unified approach to managing diverse packet transmission requirements across multiple buses.
Data Source
AI summary
In one embodiment, a packet-based system having a number of buses is stimulated using apparatus having 1) a hardware interface configured to provide data packets to the buses; 2) a plurality of hardware-based queue schedulers, each configured to schedule data packets received from a respective one of a plurality of data packet sources, in a respective one of a plurality of hardware-based queues; and 3) a hardware-based priority scheduler configured to cause each particular queue to transmit a next highest priority data packet over one of the buses, based on i) timing requirements of the next highest priority data packet in the particular queue, and ii) a determination that transmission of the next highest priority data packet in the particular queue will not delay a transmission of a higher priority data packet in another one of the hardware-based queues.