Hardware Regex Engine with Multi-Port RAM for High Throughput
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Solution Overview
Problem
Central Processing Units (CPUs) lack the processing power and bandwidth to perform regular expression processing in real time, leading to insufficient data throughput for responsive matching in various industries.
Innovation Solution
A circuit-based regular expression processing system utilizing a multi-port RAM and a hardware finite state automata (HFA) graph to efficiently process data streams, with a decoder circuit and switching circuitry for load balancing and priority management, allowing for concurrent processing of active states and path prioritization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a CPU is used to execute regular expression processing, then the system is simple and flexible, but the data throughput is insufficient (100-200 Mbps) and real-time processing capability is lacking
Solution Approach 1:
The patent replaces the software-based CPU execution model with a hardware-based regular expression processing engine. This substitution transforms the mechanical system from software instruction execution to dedicated hardware circuit operation, enabling data throughput to exceed 10 Gbps while maintaining real-time processing capability. The hardware engine includes specialized components such as a state transition unit, active state memory, and match determination unit that are specifically designed for regex operations.
Solution Approach 2:
The patent changes the operational parameters of the processing system by implementing a hardware engine with parallel processing capabilities. The system uses multiple active state memories and employs load balancing techniques to distribute processing across multiple ports of a multi-port RAM, enabling simultaneous processing of multiple regex patterns and achieving throughput rates 50-100 times higher than CPU execution.
2Adaptability or versatility
If multiple active states are tracked concurrently for complex regular expressions, then the matching capability is improved, but the memory access complexity and processing overhead increase
Solution Approach 1:
The patent segments the processing of multiple active states by organizing them into separate active state memories (AS0, AS1, AS2, etc.). Each active state memory handles specific states, and a load balancing unit distributes state transitions across these segmented memories. This segmentation reduces the complexity of memory access by allowing parallel, independent access to each segment rather than managing all states in a single complex memory structure.
Solution Approach 2:
The patent introduces a load balancing unit as an intermediary between the state transition unit and the multiple active state memories. This intermediary component manages the complexity of memory access by intelligently routing state transitions to appropriate memory ports, balancing the load across available resources, and coordinating read/write operations to prevent conflicts. The load balancing unit abstracts the complexity from the core processing logic.
3Speed
If a hardware-based regular expression engine is implemented, then the data throughput exceeds 10 Gbps and real-time processing is achieved, but the device complexity and resource requirements increase
Solution Approach 1:
The patent implements a universal hardware regular expression engine that can process multiple different regular expression patterns simultaneously. The engine uses a configurable instruction table stored in multi-port RAM that defines state transitions for various regex patterns. This universal design allows the same hardware structure to adapt to different processing requirements by loading different instruction tables, eliminating the need for separate dedicated hardware for each regex pattern and reducing overall system complexity.
Solution Approach 2:
The patent employs dynamic load balancing techniques that adapt the distribution of processing tasks across available hardware resources based on current system conditions. The load balancing unit dynamically adjusts which active state memories receive which state transitions, optimizing resource utilization in real-time. This dynamic approach allows the hardware engine to maintain high processing speeds while efficiently managing the complexity of multiple concurrent operations.
Data Source
AI summary
A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.