Hardware Rule Checking for Low-Latency Stream Processing
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Solution Overview
Problem
Conventional business rule processing systems face challenges with large and growing rule sets and data volumes, leading to high latency in decision-making, especially when handling high-speed data streams, as they are optimized for large-scale storage rather than real-time processing.
Innovation Solution
The implementation of a hardware-accelerated rule condition check system using a coprocessor, such as a field programmable gate array (FPGA), which streams data and performs rule condition checks at bus bandwidth rates, reducing latency by generating rule condition check results directly on a reconfigurable logic device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional business rule processing systems are used, then they can handle large-scale data storage, but they experience high latency in real-time processing
Solution Approach 1:
The patent replaces conventional software-based rule processing with a hardware-accelerated coprocessor system. The coprocessor uses dedicated hardware circuits to perform rule condition checks in parallel, substituting the sequential software execution model with concurrent hardware operations, thereby achieving real-time processing of high-volume data streams with minimal latency
Solution Approach 2:
The patent introduces a coprocessor as an intermediary component between the data stream source and the main processing system. This coprocessor specifically handles rule condition evaluation and generates match results, acting as a specialized mediator that offloads time-critical operations from the general-purpose system, thus reducing overall decision-making latency
2Adaptability or versatility
If more rule conditions are added to handle growing business requirements, then system versatility improves, but processing latency increases
Solution Approach 1:
The patent segments the rule processing system into distinct functional units within the coprocessor, including separate logic for different types of rule conditions (equality, inequality, range, pattern matching). Each segment can operate independently and in parallel, allowing the system to handle expanded rule sets without proportionally increasing latency, as multiple rule evaluations occur simultaneously rather than sequentially
Solution Approach 2:
The patent implements a dynamic rule processing architecture where the coprocessor can be reconfigured to handle different rule conditions and data types. The system adapts its processing logic based on the specific rules being evaluated, allowing versatile rule set expansion while maintaining optimized performance characteristics for each rule type through dynamic adjustment of processing parameters
Data Source
AI summary
Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.