Hardware SAT Solver for IC Formal Verification
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Solution Overview
Problem
Current formal verification methods for circuit designs are time-consuming and inefficient, particularly in identifying design errors or bugs, as they often rely on simulation which may miss corner-case bugs and are not exhaustively thorough.
Innovation Solution
A system combining a formal verification EDA application with a hardware prototyping platform to generate and process Conjunctive Normal Form (CNF) files, using a hardware instantiated SAT solver to physically instantiate Boolean circuits and search for counter-examples, thereby systematically verifying circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation-based verification is used, then the verification process is simpler to implement, but the verification thoroughness and bug detection capability deteriorate
Solution Approach 1:
The patent replaces traditional software-based simulation verification with a hardware-based formal verification system using FPGAs and SAT solvers. This substitution transforms the verification approach from probabilistic simulation to exhaustive mathematical analysis, achieving complete coverage of all possible input combinations and states, thereby dramatically improving verification thoroughness and bug detection capability.
Solution Approach 2:
The patent changes the fundamental parameter of verification methodology from simulation (sampling-based) to formal verification (exhaustive-based). By using SAT solvers to systematically explore all possible states and transitions, the system achieves complete verification coverage rather than relying on random or predetermined test cases, thus improving reliability.
2Productivity
If traditional formal verification software is used, then the verification can be performed on standard computing platforms, but the verification time increases considerably
Solution Approach 1:
The patent replaces software-based formal verification with hardware-based formal verification implemented on FPGAs. The hardware SAT solver processes verification problems in parallel at clock speeds millions of times faster than software execution, reducing verification time from hours or days to seconds or minutes while maintaining exhaustive analysis capability.
Solution Approach 2:
The patent transitions verification from the software execution dimension to the hardware parallel processing dimension. By implementing the SAT solver as hardware circuitry on an FPGA, the system exploits parallelism inherent in hardware architecture to simultaneously evaluate multiple verification conditions, exponentially increasing verification speed.
3Measurement precision
If hardware prototyping platform is used for formal verification, then the verification thoroughness improves with exhaustive analysis, but the device complexity and setup requirements increase
Solution Approach 1:
The patent employs an FPGA-based universal hardware platform that can be reconfigured to implement different SAT solver architectures and verify different circuit designs. The same hardware infrastructure serves multiple verification purposes, making the complexity investment worthwhile by providing a versatile, high-precision verification system that can handle various design complexities.
Solution Approach 2:
The patent segments the verification system into modular components: the FPGA hardware platform, the SAT solver logic, the circuit under verification, and the verification methodology. This segmentation allows each component to be optimized independently while maintaining overall system coherence, managing complexity through modular architecture.
Data Source
AI summary
A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for literals in the Boolean expression and the constraints of the IC chip. The formal verification application can also be configured to output the array of CNF files to a hardware prototyping platform. The hardware prototyping platform can be configured to execute a hardware instantiated SAT solver for the Boolean expression in each CNF file in the array of CNF files.