Hardware Scaler With Dynamic Filter Taps For Flexible Scaling
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Solution Overview
Problem
Existing hardware scalers are limited to standard scaling ratios and simpler filter configurations, lacking flexibility and resource efficiency, which restricts their ability to support a wide range of scaling ratios and frame sizes, leading to lower quality outputs and inefficient resource usage.
Innovation Solution
A flexible hardware scaler architecture that supports a continuous range of scaling ratios and frame sizes using a shared data path, with dynamically configurable processing units and sophisticated filter configurations, such as Lanczos filters with adjustable taps, to perform both downscaling and upscaling efficiently, minimizing resource consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If hardware scalers use standard scaling ratios and simple filter configurations, then device complexity is reduced, but adaptability and output quality deteriorate
Solution Approach 1:
The patent implements dynamically configurable filter structures where the number of taps and filter coefficients can be adjusted based on the required scaling ratio. The filter bank includes multiple configurable filters that can be selected and configured in real-time to match different scaling requirements, transforming a static simple filter into a dynamic adaptive filtering system.
Solution Approach 2:
The system changes filter parameters (number of taps, coefficients, filter type) based on the input and output frame sizes. By dynamically adjusting these parameters according to the scaling ratio, the system achieves high adaptability without requiring a completely different filter structure for each scaling scenario.
2Device complexity
If hardware scalers support only standard scaling ratios, then device complexity is reduced, but adaptability deteriorates
Solution Approach 1:
The patent designs a universal data path that can handle both downscaling and upscaling operations using the same processing units. The scalable processing units are configured to perform different functions based on the scaling ratio, eliminating the need for separate hardware paths for different scaling directions and ratios.
Solution Approach 2:
The data path incorporates dynamically reconfigurable processing units that can adapt their operation mode based on the required scaling ratio. This dynamic reconfiguration allows a single data path to support continuous scaling ratios while maintaining structural simplicity.
3Loss of energy
If hardware scalers use simple filter configurations, then resource consumption is reduced, but output quality deteriorates
Solution Approach 1:
The system employs an efficient resource allocation strategy where the full filter capability is not always utilized. For simple scaling ratios, simpler filters are used, while complex scaling ratios trigger the use of more sophisticated filters with more taps. This partial action approach optimizes resource consumption by matching filter complexity to actual requirements.
Solution Approach 2:
The filter configuration parameters (number of taps, coefficient precision, filter type) are dynamically adjusted based on the scaling complexity and quality requirements. This allows the system to use minimal resources for simple scaling tasks while providing high-quality output for complex scaling operations.
4Reliability
If hardware scalers process data through multiple stages, then processing completeness is improved, but latency increases
Solution Approach 1:
The patent combines multiple processing stages into a unified inline processing architecture where filtering, scaling, and output generation occur in a single continuous data flow. This merging eliminates intermediate buffering and stage transitions, reducing latency while maintaining complete processing functionality.
Solution Approach 2:
The system performs preliminary configuration of processing parameters based on input frame analysis before actual scaling begins. This preliminary action allows the processing pipeline to be pre-configured for optimal performance, reducing the time required during actual scaling operations.
Data Source
AI summary
Various features of a high performance hardware scaler are disclosed herein. In some embodiments, a hardware scaler comprises a first processing unit configured to perform preparation and scaling operations and a second processing unit configured to perform preparation and scaling operations. The first processing unit and the second processing unit alternatively switch between performing preparation and scaling operations when processing a current input pixel block such that the first processing unit performs scaling operations while the second processing unit performs preparation operations and the second processing unit performs scaling operations while the first processing unit performs preparation operations.