Hardware Scheduler Traversal for High-Speed Network Traffic Management
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Solution Overview
Problem
Traffic management in high-speed network ports, such as those found in optical line terminals, is challenging due to the complexity of scheduling, congestion management, and rate limiting, which traditional central processing units (CPUs) executing software alone cannot efficiently handle.
Innovation Solution
A traffic management system that includes an accelerator circuit with a memory to store a data structure, capable of traversing and updating scheduler nodes over multiple iterations, offloading tasks from the CPU to handle high-speed ports efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a CPU executing software is used for traffic management, then the system is simple to implement, but it cannot efficiently handle high-speed ports with thousands of queues and multiple scheduling parameters
Solution Approach 1:
The patent replaces the software-based CPU processing system with a hardware-based accelerator circuit. The accelerator circuit includes specialized logic units that directly implement scheduling algorithms, congestion management, and rate limiting functions in hardware, bypassing the limitations of software execution on general-purpose CPUs. This substitution enables efficient handling of high-speed ports with thousands of queues by performing traffic management operations at line rate through dedicated hardware paths.
2Productivity
If an accelerator circuit is introduced to handle high-speed ports, then traffic management efficiency improves, but device complexity increases
Solution Approach 1:
The patent segments the traffic management functionality into distinct modular components within the accelerator circuit. The scheduler is divided into multiple levels (first level scheduler, second level scheduler), each handling specific aspects of queue management. Congestion management, rate limiting, and traffic shaping are implemented as separate functional units. This segmentation allows each component to be optimized independently while working together to achieve high-throughput traffic management for high-speed ports.
3Adaptability or versatility
If multiple scheduling levels are implemented to manage thousands of queues, then resource allocation fairness improves, but the computational burden on the CPU increases
Solution Approach 1:
The patent replaces CPU-based software scheduling with hardware-based scheduling logic in the accelerator circuit. The multi-level scheduler implements hierarchical queue management where the first level scheduler handles coarse-grained queue groups and the second level scheduler manages individual queues within groups. This hierarchical approach provides scheduling flexibility for thousands of queues while performing all computational operations in hardware, eliminating the computational burden from the CPU and enabling line-rate packet processing.
Data Source
AI summary
An example traffic management system for a network device includes: a first memory storing queues of packets received by the network device; a second memory storing data of a scheduler for the queues that schedules transmission of the packets to a port of the network device; and an accelerator circuit including a third memory to store a data structure, the accelerator circuit coupled to the second memory and operable to: load, for a first iteration of a traverse operation in response to a command, a field of the data structure in the third memory with data from a first node of the scheduler; update, during the first iteration of the traverse operation, the field of the data structure in the third memory; and store, during the first iteration of the traverse operation, updated data from the field to the first node in the second memory.