Hardware Scheduling Mechanism for Dynamic Task Dependency Management

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Solution Overview

Problem

Current task management systems introduce latency due to software-based prioritization of processes, leading to inefficiencies in processor performance as they require frequent memory access and periodic updates, creating bottlenecks in scheduling.

Innovation Solution

A hardware scheduling mechanism that implements a dynamic task-dependency graph using linked lists for task data structures, where tasks are launched based on reference counters reaching a trigger value, allowing for synchronization and efficient management of dependencies without software intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If software-based task scheduling is used to manage process priorities and dependencies, then task execution order can be controlled, but latency is introduced and processor efficiency is reduced

Engineering Contradiction:
Improvetask execution orderVSAvoidscheduling latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces the software-based scheduling mechanism with a hardware-based scheduling unit. The hardware scheduling unit directly manages task priorities and dependencies through hardware circuits, eliminating the need for software kernel intervention in scheduling decisions. This substitution of software with hardware mechanics resolves the contradiction by providing both reliable task ordering control and reduced scheduling latency.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent extracts the scheduling function from the software kernel and places it in a dedicated hardware scheduling unit. By separating the scheduling functionality from the general-purpose software kernel, the system achieves specialized hardware optimization for scheduling operations, reducing latency while maintaining reliable task execution order through dedicated hardware logic.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If software kernel periodically updates priority levels to manage task scheduling, then process dependencies are maintained, but processor efficiency is slowed due to frequent memory access requests

Engineering Contradiction:
Improvedependency managementVSAvoidprocessor efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent replaces software-based priority management with hardware-based priority registers and comparison circuits. The hardware scheduling unit continuously monitors task priorities and dependencies through hardware circuits, eliminating frequent software memory access requests. This maintains reliable dependency management through hardware logic while significantly improving processor efficiency by removing the software overhead bottleneck.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware scheduling unit autonomously manages task priorities and scheduling decisions without requiring periodic software kernel intervention. The hardware system serves itself by continuously monitoring task states, comparing priorities, and dispatching tasks through dedicated hardware circuits, thereby maintaining dependency reliability while eliminating the productivity-reducing software memory access cycle.

Inventive Principle:
Principle #25Self-service

3Speed

If hardware scheduling unit executes tasks based on priority, then execution speed is improved, but software intervention is still needed to adjust priority levels

Engineering Contradiction:
Improvetask execution speedVSAvoidscheduling system complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The hardware scheduling unit is designed with universal functionality to handle both task dispatching and priority management within a single integrated hardware circuit. This multi-functional hardware design eliminates the need for separate software intervention for priority adjustments, maintaining high execution speed while reducing overall system complexity by consolidating scheduling functions in the hardware domain.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9286119B2System, method, and computer program product for management of dependency between tasks
Publication Date: 2016.03.15 NVIDIA CORP
  • US9286119B2 patent drawing
  • US9286119B2 patent drawing
  • US9286119B2 patent drawing

AI summary

A system, method, and computer program product for management of dynamic task-dependency graphs. The method includes the steps of generating a first task data structure in a memory for a first task, generating a second task data structure in the memory, storing a pointer to the second task data structure in a first output dependence field of the first task data structure, setting a reference counter field of the second task data structure to a threshold value that indicates a number of dependent events associated with the second task, and launching the second task when the reference counter field stores a particular value. The second task data structure is a placeholder for a second task that is dependent on the first task.