Hardware-Assisted Semaphore for Multi-Core Resource Access
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Solution Overview
Problem
In multi-core systems, software-based semaphores incur a performance penalty due to shared counter updates across cores, leading to decreased performance as the number of cores increases beyond four.
Innovation Solution
Implementing hardware-assisted semaphores using a memory buffer within a hardware-assisted memory pool, allowing cores to access resources without shared counters, thus eliminating cache coherency issues and maintaining performance scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based semaphores with shared counters are used to control resource access in multi-core systems, then resource access control is achieved, but system performance degrades as the number of cores increases beyond four due to cache coherency issues
Solution Approach 1:
The patent replaces the software-based semaphore mechanism with a hardware-based memory pool mechanism. Instead of using software counters that require cache coherency maintenance across cores, the invention uses hardware-managed memory buffers where each buffer represents a resource token. This substitution eliminates the need for frequent shared memory accesses and cache synchronization, thereby resolving the performance degradation while maintaining resource access control.
Solution Approach 2:
The patent introduces memory buffers as intermediary objects that mediate resource access between multiple cores. Rather than cores directly interacting through shared counters, each core obtains a memory buffer from the hardware pool as an intermediary token to access the resource. This intermediary mechanism decouples the cores from direct synchronization requirements, eliminating cache coherency problems while preserving controlled access semantics.
2Reliability
If software-based semaphores are implemented to ensure proper resource access control, then resource protection is achieved, but severe performance penalties occur as the number of cores increases
Solution Approach 1:
The patent substitutes the software semaphore timing-critical operations with hardware-based memory pool operations. The hardware automatically manages buffer allocation and deallocation, eliminating the time-consuming software loops, context switches, and cache synchronization that characterize software semaphore operations. This maintains resource protection while dramatically reducing the time loss associated with semaphore operations in multi-core systems.
3Ease of operation
If shared counters are used for semaphore implementation across multiple cores, then resource access coordination is achieved, but cache coherency maintenance causes severe performance degradation
Solution Approach 1:
The patent uses memory buffers as intermediary tokens that eliminate direct shared counter access. Instead of multiple cores reading and writing to a shared counter variable (which requires cache coherency maintenance), each core obtains a unique memory buffer from the hardware pool. The buffer itself serves as the coordination mechanism, with its presence or absence indicating resource availability, thereby maintaining ease of operation while achieving performance scalability.
Solution Approach 2:
The patent extracts the coordination function from the shared counter mechanism and embeds it directly in the hardware memory pool structure. Rather than having software manage coordination through shared variables, the hardware pool structure itself encodes the coordination state through the presence or absence of memory buffers. This extraction removes the need for cache coherency maintenance while preserving resource access coordination.
Data Source
AI summary
A method includes receiving a request to access a resource; determining a presence of a memory buffer in a hardware-assisted memory pool; and determining a response to the request to access the resource based on the presence of the memory buffer. A system includes a plurality of processors, a resource, and a hardware-assisted memory pool including a memory buffer; one of the plurality of processors receives a request to access the resource, determines a presence of the memory buffer, and determines a response to the request to access the resource based on the presence of the memory buffer.