Hardware Semaphore Power Control for AI Accelerators
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Solution Overview
Problem
Current power management techniques for AI accelerators in multi-host computing environments suffer from significant latency and complexity due to complex software-based communication and interdependencies between drivers, leading to inefficient power on/off processes.
Innovation Solution
The implementation of hardware semaphores and a hardware voter to coordinate power states and manage power on/off operations, reducing the need for software communication and simplifying the power management process across multiple hosts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based communication between drivers is used for power management, then coordination between multiple drivers can be achieved, but significant latency and system fluctuations occur due to the non-realtime nature of the Linux OS
Solution Approach 1:
The patent replaces the software-based communication mechanism (Linux pm_runtime framework) with a hardware-based mechanism (hardware semaphores and hardware voters). This substitution eliminates the latency introduced by the non-realtime Linux OS, as hardware operations execute deterministically and immediately, providing both reliable coordination and low latency for power management operations.
Solution Approach 2:
The patent introduces hardware semaphores as intermediary signaling mechanisms between drivers and the AI accelerator. These semaphores act as mediators that enable synchronized communication without requiring software-based handshaking, thus reducing latency while maintaining coordination reliability across multiple drivers.
2Adaptability or versatility
If multiple hosts each have their own power management driver, then each host can independently control power states, but memory usage and development effort increase significantly
Solution Approach 1:
The patent implements a universal hardware semaphore mechanism that serves all multiple hosts (Linux, TEE, SCP, Modem, Audio) simultaneously. Instead of requiring separate software-based power management drivers for each host, the hardware semaphores provide a common, standardized interface that all hosts can use to coordinate power states, thereby reducing overall driver complexity while maintaining multi-host adaptability.
3Reliability
If extensive handshaking communication is implemented between RV/Power driver and MMU driver, then power state coordination is achieved, but the power on/off process becomes slow and complex
Solution Approach 1:
The patent replaces the extensive software-based handshaking communication between RV/Power driver and MMU driver with hardware semaphore operations. The hardware semaphores provide atomic, lock-based coordination that is both reliable for power state management and fast in execution, eliminating the slow and complex multi-step software handshaking process.
4Manufacturing precision
If complex mapping between power path and data path controllers is implemented, then precise power control is achieved, but system complexity and development effort increase
Solution Approach 1:
The patent introduces hardware semaphores as intermediary coordination mechanisms between power path controllers and data path controllers. These semaphores simplify the complex mapping relationships by providing standardized synchronization primitives, reducing the complexity of inter-controller communication while maintaining precise power control through hardware-enforced coordination.
Data Source
AI summary
A chipset holds a first hardware semaphore to indicate that a processing subsystem is powered off. This first hardware semaphore coordinates power states between a driver and the processing subsystem. The chipset releases the first hardware semaphore when the processing subsystem is powered on. This release allows the driver to operate on a hardware component associated with the processing subsystem. The chipset attempts to acquire the first hardware semaphore by the processing subsystem before powering off. The chipset powers off the processing subsystem upon successfully acquiring the first hardware semaphore.