Hardware Simulation Controller for HDL Verification
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Solution Overview
Problem
Software-based Hardware Description Language (HDL) simulation on modern x86 server architectures is inefficient due to large semantic operation representation, poor cache utilization, and inefficient bus utilization, leading to significant processor time overhead.
Innovation Solution
A simulation hardware system with a custom logic processor and multiple memory channels is introduced, optimizing instruction sets, memory access, and parallel processing to reduce overhead and enhance performance by using memory-mapped registers and separate memory systems for different data types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-based HDL simulation is used on x86 server architectures, then simulation functionality is achieved, but processor time overhead is significant due to large semantic operation representation and poor cache utilization
Solution Approach 1:
The patent replaces the software-based simulation system with a hardware simulation system that uses a custom logic processor and dedicated hardware components. This substitution eliminates the overhead of software execution, cache management, and bus utilization inefficiencies inherent in software-based approaches, directly addressing the processor time overhead problem while maintaining simulation functionality.
Solution Approach 2:
The patent divides the simulation system into separate functional components: a custom logic processor for executing HDL instructions, dedicated memory channels for different data types, and separate memory-mapped registers for control and data. This segmentation allows each component to be optimized independently, improving overall simulation speed while reducing the time overhead associated with integrated software-based systems.
2Productivity
If HDL simulation is performed using software on x86 architecture, then simulation can be executed, but cache memory is underutilized due to non-repeated actions and fixed size cache lines
Solution Approach 1:
The patent replaces software cache management with hardware-based memory channels that are dedicated to specific data types. This hardware-level memory management eliminates the inefficiencies of software-based caching, allowing continuous and efficient memory access without the non-repeated actions that cause cache underutilization in software systems.
Solution Approach 2:
The patent implements separate memory channels for different data types (e.g., instruction memory, data memory, register memory), allowing each memory subsystem to be optimized for its specific access patterns. This local optimization improves cache utilization by ensuring that each memory type is accessed efficiently according to its specific requirements, rather than using a unified cache system.
3Productivity
If traditional software simulation kernel is used, then HDL simulation can be performed, but bus effective utilization is poor due to fixed size cache lines and mismatch between bytes used and bytes read
Solution Approach 1:
The patent replaces software-based bus management with hardware memory channels that have dedicated, optimized access paths. This hardware-level approach eliminates the fixed-size cache line constraints of software systems, allowing variable-sized data transfers that match actual memory access requirements, thereby improving bus effective utilization.
Solution Approach 2:
The patent implements dynamic memory access patterns through hardware memory channels that can adapt to different data sizes and access requirements. Unlike fixed-size cache lines in software systems, the hardware memory channels can efficiently transfer variable amounts of data, improving bus utilization by matching the actual bytes read to the bytes needed for simulation operations.
Data Source
AI summary
Systems and methods of using hardware to simulate software, specifically the semantic operations defined in HDL simulation languages. Traditional software HDL simulation kernel operations of advancing time, activating threads in response to notified events, and scheduling those threads of execution are handled via a simulation controller. The simulation controller is comprised of a timing wheel, an event-processor, a thread/process dispatch engine, a token processor, and a resource-allocator. These components work together with a control logic component to perform the semantic operations of an HDL software kernel.