Hardware Simulation Partitioning for Multiprocessor Performance

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional hardware simulation and verification solutions for complex integrated circuits face performance bottlenecks due to increasing size and complexity, as traditional methods like rewriting software or using parallelizing compilers are impractical and often degrade performance due to synchronization issues.

Innovation Solution

Partitioning the hardware simulation and verification solution into modules such as a simulation kernel, value change dump, functional coverage, toggle coverage, assertion engine, and testbench, allowing these modules to be executed in parallel across multiple processors with minimal communication and synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the hardware simulation and verification solution is executed on a single processor, then the software complexity is maintained at a manageable level, but the processing speed and performance are insufficient due to the increasing size and complexity of integrated circuits

Engineering Contradiction:

Improveprocessing speedVSAvoidsoftware complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The hardware simulation and verification solution is divided into multiple independent modules that can be executed in parallel on different processors. Each module handles a specific aspect of the simulation or verification process, allowing the system to scale across multiple processors without proportionally increasing inter-module communication complexity.

Inventive Principle:

Principle #1Segmentation

2Productivity

If the software is rewritten from scratch to enable parallel execution, then parallel processing capability is achieved, but the development cost and time are enormous

Engineering Contradiction:

Improveparallel processing capabilityVSAvoiddevelopment cost

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

Rather than rewriting the entire software system, the invention segments the existing hardware simulation and verification solution into modular components that can be independently executed in parallel. This approach enables parallel processing capability while avoiding the enormous cost of complete software rewriting.

Inventive Principle:

Principle #1Segmentation

3Productivity

If a parallelizing compiler is used to improve performance, then some parallelization is achieved, but the performance improvement is limited because sophisticated parallelizing compilers often fail to exploit parallelization opportunities in complex software

Engineering Contradiction:

Improveperformance improvementVSAvoidparallelization effectiveness

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The software is explicitly segmented into distinct modules that represent natural parallelization opportunities in hardware simulation and verification. This manual segmentation approach is more effective than automated parallelizing compilers because it leverages domain knowledge to identify and exploit parallelization opportunities that general-purpose compilers may miss.

Inventive Principle:

Principle #1Segmentation

4Productivity

If only a small portion of the software is parallelized, then implementation complexity is reduced, but performance improvement is negligible due to Amdahl's law

Engineering Contradiction:

Improveperformance improvementVSAvoidparallelization scope

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The software is comprehensively segmented into multiple parallelizable modules, maximizing the proportion of code that can execute in parallel. This extensive segmentation overcomes Amdahl's law by ensuring that the majority of the computation can be distributed across multiple processors, thereby achieving significant performance improvement.

Inventive Principle:

Principle #1Segmentation

5Productivity

If the software is partitioned into different pieces for parallel execution, then parallel processing is enabled, but performance degrades if the different pieces require large amounts of synchronization

Engineering Contradiction:

Improveparallel processing capabilityVSAvoidsynchronization overhead

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The software is segmented into modules with well-defined interfaces and minimal shared state, reducing the need for synchronization. Each module operates relatively independently, allowing parallel execution with minimal coordination overhead between processors.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Synchronization requirements are extracted and minimized by designing modules that can operate independently. The invention identifies and removes unnecessary synchronization points, allowing modules to execute in parallel without requiring frequent coordination.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS9536027B2Executing a hardware simulation and verification solution

Publication Date: 2017.01.03 SYNOPSYS INC

AI summary

One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.