Hardware State Machine for Low-Power Cardiac Pacing

The patent segments the pacing decision-making process into two parts: a hardware-based state machine that handles real-time timing and state transitions (consuming minimal power), and a microprocessor that only executes when necessary to load new pacing modes or respond to complex sensor inputs. This segmentation allows the system to maintain flexibility through programmable modes while dramatically reducing continuous power consumption by keeping the microprocessor in a low-power state during normal operation.

The patent introduces a hardware-based state machine as an intermediary between the microprocessor and the pacing output generation. This state machine acts as a mediator that continuously monitors device state and automatically executes appropriate pacing actions based on pre-defined transitions, eliminating the need for the microprocessor to continuously execute instructions. The microprocessor only interacts with the state machine when mode changes are required, thus reducing power consumption while maintaining flexibility.

The patent segments the timing-critical functions from the flexible but power-consuming microprocessor execution. The hardware state machine segments out all timing-sensitive state transitions and pacing decisions, executing them through dedicated hardware logic that operates independently of microprocessor instruction cycles. This ensures consistent, jitter-free timing while the microprocessor handles only the flexible mode selection in a separate, non-time-critical path.

The patent replaces the software-based timing mechanism (microprocessor instruction execution) with a hardware-based state machine that uses dedicated circuitry for timing and state transitions. This substitution of mechanical/software system with hardware circuitry eliminates timing variability caused by instruction execution variations, while the programmable nature of the state machine transitions maintains device flexibility.