Hardware Synchronizer Modules for Multithreaded Processor Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-threaded processor synchronization methods require significant software effort and lead to inefficient code density and increased synchronization delays due to the need for extensive memory accesses and repeated thread creation/termination for synchronization.
Innovation Solution
Implementing hardware synchronizer modules with logic for barrier synchronization, allowing for simplified thread synchronization by associating and de-associating threads with synchronizer modules, reducing the need for synchronization code and memory accesses, and enabling flexible resource sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier synchronisation is implemented in software, then thread synchronisation can be achieved, but code density decreases and synchronisation delay increases
Solution Approach 1:
The patent replaces software-based barrier synchronisation mechanisms with hardware-based synchroniser modules. The execution unit includes dedicated synchroniser modules that automatically manage thread synchronisation through hardware logic, eliminating the need for software-coded barrier instructions and associated memory accesses, thus improving code density while maintaining synchronisation reliability
Solution Approach 2:
The patent introduces synchroniser modules as intermediary hardware components between the execution unit and memory system. These modules act as mediators that track thread execution states and automatically pause/resume threads at synchronisation points without requiring software intervention or memory accesses, thereby reducing synchronisation delay and improving code density
2Reliability
If barrier synchronisation is implemented in software, then thread synchronisation can be achieved, but synchronisation delay increases
Solution Approach 1:
The patent replaces software-based barrier synchronisation with hardware-based synchroniser modules that operate at the execution unit level. This substitution eliminates the need for memory accesses required by software implementations, significantly reducing synchronisation delay while maintaining reliable thread synchronisation through dedicated hardware logic
Solution Approach 2:
The synchroniser modules perform preliminary tracking of thread execution states and automatically prepare synchronisation actions before threads reach synchronisation points. This preliminary hardware-based preparation eliminates the need for runtime memory accesses and software processing, reducing synchronisation delay while ensuring reliable thread coordination
3Reliability
If synchronisation code is extensively coded into threads, then thread synchronisation can be achieved, but code complexity increases
Solution Approach 1:
The patent replaces complex software-coded synchronisation logic with simplified hardware-based synchroniser modules. The execution unit includes dedicated synchroniser modules that automatically manage thread association and synchronisation through hardware logic, eliminating the need for developers to code complex barrier synchronisation sequences, thus reducing code complexity while maintaining synchronisation reliability
Solution Approach 2:
The synchroniser modules provide self-service functionality by automatically tracking thread states, managing synchronisation points, and coordinating thread pausing/resuming without requiring software intervention. This self-managing hardware approach simplifies the code structure while ensuring reliable thread synchronisation
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The invention provides a processor comprising an execution unit arranged to execute multiple program threads, each thread comprising a sequence of instructions, and a plurality of synchronisers for synchronising threads. Each synchroniser is operable, in response to execution by the execution unit of one or more synchroniser association instructions, to associate with a group of at least two threads. Each synchroniser is also operable, when thus associated, to synchronise the threads of the group by pausing execution of a thread in the group pending a synchronisation point in another thread of that group.