Hardware Task Scheduling for Concurrent Accelerator Dependencies
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Solution Overview
Problem
Current hardware thread schedulers lack the flexibility needed for efficient scheduling of image and vision processing tasks in advanced driver assistance systems (ADAS), particularly in managing concurrent threads and data dependencies between hardware accelerators.
Innovation Solution
A software configurable hardware thread scheduler (HTS) is introduced to manage execution of threads on multiple hardware accelerators, enabling flexible scheduling and concurrent processing of tasks with low-overhead synchronization and data sharing, using a messaging layer for producer-consumer dependencies and blocking circuits to control data flow between accelerators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current hardware thread schedulers are used, then scheduling of single thread is provided, but flexibility for concurrent threads and data dependencies is insufficient
Solution Approach 1:
The scheduler is divided into multiple independent hardware task schedulers, each dedicated to a specific hardware accelerator. This segmentation allows concurrent execution of multiple threads on different accelerators while maintaining manageable complexity through modular design. Each scheduler independently manages its assigned accelerator, enabling flexible thread scheduling across the entire system.
Solution Approach 2:
The hardware task schedulers are designed with multi-functionality to handle various thread configurations and data dependency patterns. The schedulers can dynamically adapt to different task requirements, supporting both sequential and concurrent execution modes, thereby providing versatility without requiring completely separate scheduling mechanisms for each scenario.
2Productivity
If multiple hardware accelerators are used concurrently, then processing throughput is improved, but data flow control and synchronization overhead increases
Solution Approach 1:
A blocking circuit is introduced as an intermediary component between hardware accelerators to manage data flow control. This blocking circuit acts as a mediator that coordinates data transfers and synchronizes operations between concurrent accelerators, reducing the synchronization overhead that would otherwise result from direct peer-to-peer communication requirements.
Solution Approach 2:
The scheduler incorporates feedback mechanisms that monitor task completion and data availability status. This feedback allows the system to dynamically adjust scheduling decisions and data flow routing in real-time, optimizing throughput while minimizing synchronization delays through adaptive response to current system state.
3Reliability
If pipeline flushing is used to manage data dependencies, then data integrity is maintained, but processing efficiency is reduced
Solution Approach 1:
The system dynamically manages data dependencies between pipeline stages through configurable blocking circuits rather than using fixed pipeline flushing. This dynamic approach allows the system to adapt data flow control to actual dependency requirements, maintaining data integrity only when necessary while enabling continuous processing when dependencies are satisfied, thus improving overall processing efficiency.
Data Source
AI summary
A data processing device includes a plurality of hardware accelerators, a scheduler circuit, and a blocking circuit. The scheduler circuit is coupled to the plurality of hardware accelerators, and includes a plurality of hardware task schedulers. Each hardware task scheduler is coupled to a corresponding hardware accelerator, and is configured to control execution of the task by the hardware accelerator. The blocking circuit is coupled to the plurality of hardware accelerators and configured to inhibit communication between a first hardware accelerator and a second hardware accelerator of the plurality of hardware task schedulers.