Hardware Thread Management Circuit for Scalable Accelerator Offloading
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Solution Overview
Problem
Conventional software-based thread management in parallel programming architectures is inefficient for applications requiring a large number of threads to be offloaded for execution by hardware accelerator circuits, leading to cumbersome pre-allocation and re-allocation of thread identifiers, which is not scalable.
Innovation Solution
A processing system with a thread management circuit that stores a thread identifier table and a thread completion table, dynamically allocating and re-allocating thread identifiers, and communicating with processor cores and accelerator circuits to manage thread execution and integration, thereby avoiding software-based allocation challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based allocation of thread identifiers is used, then thread management is implemented, but scalability deteriorates for applications requiring a large number of threads
Solution Approach 1:
The patent replaces software-based thread identifier allocation with a hardware thread management circuit that uses dedicated hardware tables (thread identifier table and thread completion table) to manage threads. This substitution of software mechanisms with hardware circuits enables scalable thread management for applications requiring large numbers of threads, as the hardware circuit can dynamically allocate and track thread identifiers without the limitations of software pre-allocation approaches.
2Speed
If software-based pre-allocation of thread identifiers is used, then thread tracking is enabled, but execution speed deteriorates due to manual allocation and re-allocation operations
Solution Approach 1:
The hardware thread management circuit performs self-service by automatically allocating thread identifiers from the thread identifier table and tracking thread completion status without requiring software intervention. The circuit autonomously manages the allocation process, updates thread completion tables, and facilitates thread joining operations, thereby eliminating the time-consuming manual allocation and re-allocation operations inherent in software-based approaches.
3Adaptability or versatility
If hardware thread management circuit is introduced, then scalability is improved, but device complexity increases
Solution Approach 1:
The patent merges the thread management functions into an integrated hardware circuit that combines multiple functionalities: thread identifier allocation, thread completion tracking, and thread joining coordination. By consolidating these functions into a single unified hardware thread management circuit with shared memory tables, the system achieves scalable thread management while minimizing the increase in overall device complexity compared to separate dedicated components for each function.
Data Source
AI summary
A thread management circuit of a processing system stores a thread identifier table and a thread completion table. The thread management circuit receives, from a processor core, a request for execution of a portion of an application by an accelerator circuit. The thread management circuit allocates a thread identifier available in the thread identifier table to the processor core for the execution of the portion by the accelerator circuit. The thread management circuit communicates a response and an acceleration request, both including the allocated thread identifier, to the processor core and the accelerator circuit, respectively. The thread management circuit communicates a thread joining response to the processor core based on a received thread joining request and an indication by the thread completion table that the execution of the portion by the accelerator circuit is complete. The executed portion is integrated with the application based on the thread joining response.