Hardware Thread Scheduler for Concurrent Vision Processing
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Solution Overview
Problem
Current hardware thread schedulers lack the flexibility needed for efficient scheduling of image and vision processing tasks in advanced driver assistance systems (ADAS), which rely on computer vision processing and require concurrent execution of multiple threads on hardware accelerators.
Innovation Solution
A software-configurable hardware thread scheduler that manages the execution of concurrent threads across multiple hardware data processing nodes, including hardware accelerators and software tasks, using a scheduler crossbar to synchronize tasks and enable flexible scheduling of consumer and producer threads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single thread is scheduled on hardware accelerators using conventional hardware thread schedulers, then the system maintains simple scheduling logic, but the system lacks the flexibility and concurrency needed for efficient image and vision processing in ADAS
Solution Approach 1:
The system divides the hardware accelerators into multiple subsets, with each subset dedicated to a specific thread. This segmentation allows concurrent execution of multiple threads while maintaining simple scheduling logic within each thread's dedicated subset, resolving the contradiction between scheduling flexibility and scheduler complexity
Solution Approach 2:
The patent introduces a new dimension of thread-level parallelism by enabling concurrent execution of multiple threads on different subsets of hardware accelerators. This dimensional expansion allows the system to achieve both flexibility (through multiple concurrent threads) and simplicity (through dedicated subsets for each thread)
2Productivity
If multiple threads are executed concurrently on hardware accelerators, then the system achieves better performance for vision processing tasks, but the scheduling complexity increases significantly
Solution Approach 1:
By segmenting hardware accelerators into dedicated subsets for each thread, the system enables concurrent execution of multiple threads (improving productivity) while keeping each subset's scheduling logic simple (avoiding complexity escalation). Each subset operates independently with its own simple scheduler
Solution Approach 2:
Each dedicated subset of hardware accelerators autonomously executes its assigned thread with minimal external scheduling intervention. The subsets self-manage their task execution, reducing the overall scheduling complexity while maintaining high productivity through concurrent operation
3Productivity
If hardware accelerators are dedicated to single threads, then the scheduling logic remains simple, but the system cannot efficiently utilize all hardware resources for concurrent vision processing tasks
Solution Approach 1:
The system segments hardware accelerators into multiple dedicated subsets, where each subset is assigned to a specific thread. This segmentation enables concurrent execution of multiple threads (improving productivity) while maintaining simple scheduling logic within each subset (preserving single-thread simplicity)
Solution Approach 2:
The hardware accelerator system achieves multi-functionality by supporting concurrent execution of multiple threads across different subsets. Each subset can be independently configured and executed, allowing the system to handle multiple vision processing tasks simultaneously while maintaining the simplicity of single-thread scheduling logic
Data Source
AI summary
A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node is configured to execute a task, and a hardware thread scheduler coupled to the plurality of hardware data processing nodes, the hardware thread scheduler configurable to concurrently execute a first thread of tasks and a second thread of tasks on the plurality of hardware data processing nodes.