Hardware Thread Scheduler for Multi-Processor Systems

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional scheduling mechanisms in multi-processor systems are slow, leading to reduced performance due to inefficient thread execution scheduling.

Innovation Solution

A thread execution scheduler that performs instruction-by-instruction scheduling and determines dynamic priorities for threads based on the amount of work to be done and the time from a deadline, using hardware context switching and a hardware scheduler to optimize thread execution in a multi-processing system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional scheduling mechanisms are used, then device complexity is reduced, but productivity deteriorates due to slow scheduling speed

Engineering Contradiction:
Improvescheduling speedVSAvoidscheduler complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces software-based scheduling mechanisms with a hardware scheduler that performs instruction-by-instruction scheduling. This substitution of mechanical/hardware system for software system directly increases scheduling speed while managing complexity through dedicated hardware circuitry designed for this specific function.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware scheduler acts as an intermediary component between the processors and the operating system, handling thread scheduling at the hardware level. This intermediary approach allows fast hardware-based scheduling decisions while still enabling software-based management and control when needed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If instruction-by-instruction scheduling is implemented, then productivity is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidscheduler structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The hardware scheduler is divided into multiple specialized components including a priority calculator that determines thread priorities, a scheduler that selects next instructions, and context switch hardware that manages thread state transitions. This segmentation allows each component to perform its specific function efficiently while keeping individual component complexity manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically changes thread priorities based on real-time parameters such as deadline urgency and remaining work量. The priority calculator continuously updates priority values as thread execution progresses, allowing the scheduler to adapt to changing conditions and optimize processing efficiency without requiring complex reconfiguration.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If dynamic priority determination is used, then productivity is enhanced, but measurement precision requirements increase

Engineering Contradiction:
Improvethread execution efficiencyVSAvoidwork estimation accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The priority calculator uses feedback from thread execution progress to dynamically adjust priorities. It continuously monitors how much work remains and how much time is left, then updates priority values accordingly. This feedback mechanism allows the system to make accurate scheduling decisions even with initial estimation uncertainties, as priorities are refined in real-time based on actual execution data.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Thread priorities are not fixed but dynamically change during execution based on remaining work and time constraints. The system transitions from static priority assignment to dynamic priority adjustment, allowing threads to be rescheduled as conditions change, which improves overall system productivity while managing measurement requirements through continuous adaptation.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7802255B2Thread execution scheduler for multi-processing system and method
Publication Date: 2010.09.21 STMICROELECTRONICS INT NV
  • US7802255B2 patent drawing
  • US7802255B2 patent drawing
  • US7802255B2 patent drawing

AI summary

A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes at least one hardware scheduler capable of scheduling execution of the plurality of threads by the plurality of processors. The at least one hardware scheduler is capable of scheduling execution of the threads by performing instruction-by-instruction scheduling of the threads.