Hardware Thread Scheduler for Flexible ADAS Task Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current hardware thread schedulers lack the flexibility needed for efficient scheduling of image and vision processing tasks in advanced driver assistance systems (ADAS), which rely on computer vision processing and require concurrent execution of multiple tasks across hardware accelerators and software processors.
Innovation Solution
A software-configurable hardware thread scheduler (HTS) is introduced, which includes multiple data processing nodes and task schedulers connected via a hardware scheduler crossbar, utilizing pending and decrement signals to manage the execution of threads across hardware accelerators and DMA channels, enabling flexible scheduling of tasks and concurrent thread execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single thread scheduler is used in hardware thread schedulers, then device complexity is reduced, but adaptability and versatility are insufficient for concurrent execution of multiple tasks
Solution Approach 1:
The hardware thread scheduler is segmented into multiple independent task schedulers (first task scheduler, second task scheduler, etc.), each capable of managing a separate thread of tasks. This segmentation allows concurrent execution of multiple task threads while maintaining individual control over each scheduler, resolving the contradiction between scheduling flexibility and device complexity.
Solution Approach 2:
Each task scheduler in the hardware thread scheduler is designed with universal functionality to handle different types of data processing nodes (hardware accelerators, software processors, DMA channels). This multi-functionality enables a single scheduler structure to manage diverse computing resources across multiple threads, achieving adaptability without proportionally increasing complexity.
2Productivity
If multiple task schedulers are introduced to enable concurrent thread execution, then productivity and scheduling efficiency are improved, but device complexity increases
Solution Approach 1:
Multiple task schedulers are merged into a unified hardware thread scheduler structure that shares common control logic and resource management mechanisms. This merging approach enables concurrent task execution across multiple schedulers while avoiding the complexity of completely independent scheduler implementations, as they operate under a coordinated framework.
Solution Approach 2:
A control unit acts as an intermediary between multiple task schedulers and the various data processing nodes (hardware accelerators, software processors, DMA channels). This mediator coordinates task allocation and scheduler operations, enabling high productivity through concurrent execution while managing complexity through centralized control logic.
3Adaptability or versatility
If hardware accelerators and software processors are integrated in the data processing system, then adaptability is improved, but device complexity increases
Solution Approach 1:
Different data processing nodes (hardware accelerators, software processors, DMA channels) are assigned specific functional characteristics and optimization profiles suited to their nature. Hardware accelerators handle computationally intensive parallel operations, while software processors manage complex control logic and sequential tasks. This local quality differentiation enables the system to achieve high adaptability for diverse vision processing tasks while managing overall complexity through specialized design.
Data Source
AI summary
Systems and method are provided for flexibly configuring task schedulers and respectively associated data processing nodes to execute threads of tasks using a hardware thread scheduler (HTS). The data processing nodes may be hardware accelerators, channels of a direct memory access circuit and external nodes such as a processor executing software instructions. Each hardware accelerator is coupled to a respective hardware task scheduler, each channel is coupled to a respective channel task scheduler, and each external node is coupled to a proxy task scheduler. The task schedulers communicate via pending and decrement signals with a hardware scheduler crossbar. With this arrangement, the HTS couples a first subset of task schedulers in a first data processing order with the associated data processing nodes performing the tasks, and couples a second subset of task schedulers in a second data processing order with the associated data processing nodes performing the tasks.