Hardware Thread Scheduling Circuit for Audio Processing
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Solution Overview
Problem
Software-based thread scheduling in multi-threaded processor cores incurs high processing overhead, limiting processing bandwidth and efficiency, especially at higher sampling rates for audio signal processing.
Innovation Solution
A hardware scheduling circuit is configured to prioritize and manage the execution of threads based on availability of data samples and thread priority, using state machines to pause and resume threads efficiently, reducing overhead and improving resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based thread scheduling is used in multi-threaded processor cores, then thread management flexibility is improved, but processing overhead increases and processing bandwidth decreases
Solution Approach 1:
The patent replaces software-based thread scheduling with a hardware scheduling circuit that uses state machines to manage thread execution. This substitution of mechanical/hardware control for software control eliminates the processing overhead associated with software scheduling while maintaining thread management flexibility through configurable priority levels and state machine logic.
Solution Approach 2:
The patent introduces a hardware scheduling circuit as an intermediary between the execution unit and multiple threads. This intermediary circuit manages thread selection and switching based on priority indications and data sample availability, freeing the main processor from scheduling overhead while ensuring efficient resource allocation.
2Ease of operation
If software-based thread scheduling is used, then scheduling control flexibility is improved, but processing efficiency deteriorates
Solution Approach 1:
The patent replaces software scheduling mechanisms with hardware-based state machines that automatically manage thread execution. This hardware implementation provides scheduling control flexibility through programmable priority levels and state transitions while eliminating the efficiency losses associated with software intervention in the execution path.
Solution Approach 2:
The hardware scheduling circuit autonomously manages thread selection and switching based on priority indications and data availability without requiring software intervention. The state machines self-regulate thread execution by transitioning between states based on predefined conditions, thereby maintaining scheduling flexibility while maximizing processing efficiency.
3Productivity
If hardware scheduling circuit is used to prioritize and manage threads, then processing overhead is reduced, but device complexity increases
Solution Approach 1:
The patent divides the scheduling function into discrete state machines, each handling specific thread priorities or scheduling states. This segmentation of the scheduling logic into modular state machine components reduces overall circuit complexity by enabling independent design, verification, and optimization of individual scheduling states while maintaining low processing overhead.
Data Source
AI summary
A hardware scheduling circuit may receive priority indications for a plurality of threads for processing, by an execution unit, multiple data samples associated with a signal. A particular thread of the plurality of threads may be scheduled for execution by the execution unit based on a priority of the particular thread and based on an availability of some of the multiple data samples that are to be processed by the particular thread.