Hardware Thread Scheduling Device for Multi-Core Processors
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Solution Overview
Problem
In multi-core processor systems, existing scheduling methods often overlook hardware considerations, leading to performance penalties due to variability among cores, as they schedule threads independently without accounting for core-specific metrics like performance or power usage.
Innovation Solution
A thread scheduling device utilizes usage counters, core rank maps, and thread priority to determine the best core for scheduling, considering metrics like performance and power consumption, and performs cost-benefit analysis for thread migration to optimize core utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If threads are scheduled independently of hardware considerations, then scheduling simplicity is maintained, but system performance deteriorates due to core variability
Solution Approach 1:
The patent introduces a hardware-based thread scheduling device as an intermediary component between the operating system and the cores. This device includes usage counters, a core rank map, and scheduling logic that automatically considers hardware factors like core availability and performance characteristics, thereby resolving the contradiction by maintaining scheduling simplicity while improving system performance through hardware-aware decisions
2Productivity
If hardware-based scheduling is implemented, then system performance improves through optimized core selection, but device complexity increases due to additional scheduling components
Solution Approach 1:
The patent replaces the software-based scheduling mechanism with a hardware-based scheduling device that uses dedicated circuits for usage counters, core rank maps, and scheduling logic. This substitution improves system performance by enabling faster, more precise hardware-aware scheduling decisions while consolidating scheduling functions into a dedicated hardware module, thereby managing complexity through specialization
3Productivity
If thread migration is performed without cost-benefit analysis, then core utilization improves, but energy consumption increases due to unnecessary migrations
Solution Approach 1:
The patent implements a feedback mechanism where the thread scheduling device continuously monitors usage counters that track core availability and performance metrics. Before initiating thread migration, the device performs cost-benefit analysis by comparing the expected performance gain against the migration cost, using real-time feedback from the usage counters to make informed decisions that improve core utilization while avoiding unnecessary migrations that would waste energy
Data Source
AI summary
A method, device, and system are disclosed. In one embodiment the method includes scheduling a thread to run on first core of a multi-core processor. The determination as to which core the thread is scheduled on uses one or more processes. These processes may include ranking all of the cores specific to a workload of the thread, establishing a current utilization of each core of the multi-core processor, and calculating an inter-core migration cost for the thread.