Hardware Time Stamping for Network Jitter Measurement
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Solution Overview
Problem
Current network testing systems introduce latency and inaccuracies in measuring jitter and other timing metrics due to processor-dependent time stamping, which is inadequate for evaluating high-quality voice and streaming media communications.
Innovation Solution
Implementing hardware time stamping in network communications units separate from processors, allowing for precise and immediate addition of timing information to data units, reducing processor-induced latency and enhancing jitter measurement accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If processor-based time stamping is used, then the system is simpler to implement, but the measurement precision and timing accuracy deteriorate due to latency
Solution Approach 1:
The time stamping function is extracted from the processor and implemented as a separate hardware circuit within the network interface card. This dedicated hardware time stamping unit operates independently from the processor, eliminating processor-induced latency and achieving tens of nanoseconds timing accuracy while keeping the overall system architecture manageable through functional separation.
Solution Approach 2:
A hardware intermediary circuit is introduced between the network medium and the processor to perform time stamping operations. This intermediate hardware layer captures timing information directly at the network interface level before data is passed to the processor, thereby preserving precise timing measurements without requiring complex processor-based software solutions.
2Productivity
If hardware time stamping is implemented, then the productivity and speed of timing measurements improve, but the device complexity increases
Solution Approach 1:
The time stamping function is extracted from the processor and implemented as a separate hardware circuit within the network interface card. This dedicated hardware time stamping unit operates independently from the processor, eliminating processor-induced latency and achieving tens of nanoseconds timing accuracy while keeping the overall system architecture manageable through functional separation.
3Reliability
If processor-based time stamping is used, then the device complexity is lower, but the reliability of timing measurements deteriorates due to processor latency and jitter
Solution Approach 1:
The time stamping function is extracted from the processor and implemented as a separate hardware circuit within the network interface card. This dedicated hardware time stamping unit operates independently from the processor, eliminating processor-induced latency and achieving tens of nanoseconds timing accuracy while keeping the overall system architecture manageable through functional separation.
Data Source
AI summary
Hardware time stamping is disclosed. In a method, a transmit time stamp may be added to an outgoing data unit in hardware prior to transmitting the outgoing data unit over a communications medium. The outgoing data unit may be received from a processor and may be intended for a node. The outgoing data unit may be transmitted over the communications medium to the node. An incoming data unit may be received over the communications medium. A receive time stamp may be added to the incoming data unit in hardware before the incoming data unit is provided to the processor. The method may be achieved on a hardware device included on a board in a network testing system.