Hardware Timer Interrupts for Multi-Tasking in Single-Tasking Systems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing single-tasking systems lack the capability to implement multi-tasking due to the absence of task-related management and services such as task start/termination, scheduling, and inter-process communication mechanisms.
Innovation Solution
A method and device that allocate a hardware timer to a slave task on a CPU, configuring it to generate periodic interrupts, which segment the slave task into multiple transaction layers, allowing only one step to be executed per interrupt, using reentrant stepped functions and step count variables to manage execution and termination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-tasking system is used to achieve multi-tasking capability, then task management and concurrent execution are enabled, but scheduling overhead and system resource consumption increase significantly
Solution Approach 1:
The slave task is segmented into multiple transaction running layers, with each layer representing a discrete executable unit. This segmentation allows the system to manage multiple tasks through simple sequential execution of layers rather than complex concurrent task scheduling, thereby enabling multi-tasking capability while avoiding the overhead of traditional multitasking mechanisms.
Solution Approach 2:
The hardware timer generates periodic interrupts to trigger the execution of slave task layers. This periodic action mechanism provides a simple, regular schedule for task execution without requiring complex scheduling algorithms, enabling concurrent execution of master and slave tasks while minimizing scheduling overhead.
2Productivity
If a multi-tasking system is used to achieve task concurrency, then multiple tasks can execute simultaneously, but system resource consumption increases
Solution Approach 1:
The invention extracts only the essential timing and triggering functions needed for multi-tasking from a full operating system. By using a simple hardware timer for periodic interrupts rather than a complete multitasking OS, the system achieves task concurrency while eliminating the substantial resource consumption associated with full operating system overhead.
Solution Approach 2:
Each transaction running layer is designed as a lightweight, short-lived execution unit that can be quickly instantiated and executed. These simple layer structures consume minimal resources compared to full task contexts, enabling efficient concurrent execution with low system resource consumption.
3Adaptability or versatility
If a multi-tasking system is used to manage multiple tasks, then task scheduling is enabled, but management and maintenance complexity increases
Solution Approach 1:
By segmenting tasks into discrete transaction running layers with clear entry and exit points, the system simplifies task management and maintenance. Each layer is an independent, manageable unit that can be individually modified, debugged, and maintained without affecting other layers, thereby reducing overall system complexity while maintaining scheduling capability.
4Device complexity
If existing single-tasking system architecture is used, then system simplicity and low resource consumption are maintained, but multi-tasking capability is absent
Solution Approach 1:
The invention nests multiple transaction running layers within the single-tasking system architecture. The slave task layers are embedded within the master task execution flow, triggered by hardware timer interrupts. This nesting approach enables multi-tasking capability while preserving the simplicity of the underlying single-tasking system architecture.
Solution Approach 2:
The hardware timer acts as an intermediary between the simple single-tasking architecture and the need for multi-tasking. It provides periodic interrupts that trigger slave task execution without requiring the system to adopt complex multitasking OS structures, thereby bridging the gap between architectural simplicity and multi-tasking capability.
Data Source
AI summary
Disclosed are a method, a device, and a single-tasking system for implementing multi-tasking in a single-tasking system. The method includes: performing a master task; allocating a hardware timer to a slave task on a central processing unit (CPU); configuring an interrupt period of the hardware timer; and generating, by the hardware timer, a hardware interrupt periodically based on the interrupt period to trigger the performance of the slave task. Therefore, independent and concurrent execution of the master task and slave task can be achieved in a single-tasking system, without the need to add an unwieldy multitasking scheduling framework to the operating system. Furthermore, the slave task is executed only when the hardware timer generates hardware interrupts, so less system resources will be consumed and the unwieldy inter-process communication mechanisms as adopted in traditional multi-tasking systems won't be needed. Example inter-process communication mechanisms may include, semaphores, spinlocks, etc.